Programming Model; Table 6-1 Reset Module Pin And Signal Descriptions; Clk32; Reset_In - Motorola DragonBall MC9328MX1 Reference Manual

Signal Name

CLK32

POR
RESET
TRST

WAT_RESET

CORE_TRST

HARD_ASYN_RESET

HRESET

RESET_DRAM

6.2 Programming Model

The Reset Source Register (RSR), the only register in the reset module, can be written to or read by the
ARM920T processor through the IP bus interface.

6.2.1 Reset Source Register (RSR)

The Reset Source Register is a 16-bit read-only register used by the ARM920T processor to determine the
source of the last MC9328MX1. hardware reset. The source of the last hardware reset is defined in
Table 6-2 and Table 6-3 on page 6-4.
If several sources' signals overlap and if the signals are released during the same CLK32 cycle (which also
causes the assertion of the RESET_OUT signal), only the highest-priority event is registered by the RSR
using the following priority order:
1. POR signal
2. Qualified external reset signal
3. Watchdog signal
Otherwise, the last signal that is released is honored.
MOTOROLA
Table 6-1. Reset Module Pin and Signal Descriptions
Direction
IN 32 kHz Clock—A 32 kHz clock signal derived from the input crystal
oscillator circuit in the PLL.
IN Power-On Reset—An internal active high Schmitt trigger signal from the
POR pin. The POR signal is normally generated by an external RC circuit
designed to detect a power-up event.
IN Reset—An external active low Schmitt trigger signal from the
pin. When this signal goes active, all modules (except the reset module and
the clock control module) are reset.
IN Test Reset Pin—An external active low signal from the TRST pin. The Test
Reset Pin is used to asynchronously initialize the JTAG controller.
IN Watchdog Timer Reset—An active low signal generated by the watchdog
timer when a time-out period has expired.
OUT Core Test Reset—An active low signal that resets the JTAG module and
the ETM.
OUT Hard Asynchronous Reset—An active low signal that resets all peripheral
modules except the watchdog timer module. The rising edge of this signal is
synchronous with HCLK.
OUT Hard Reset—An active low signal that resets the ARM920T processor and
the watchdog timer module.This signal is deasserted during the low phase
of HCLK. This signal also appears on the RESET_OUT pin of the
MC9328MX1.
OUT DRAM Reset—An active low signal that resets the DRAM controller.
Reset Module
Programming Model
Signal Description

RESET_IN

6-3