D Memory Registers (A And B); W-Size Registers; Table 13-11 W-Size Registers Description - Motorola DragonBall MC9328MX1 Reference Manual

DMA Controller

13.4.2 2D Memory Registers (A and B)

The two sets of 2D memory registers allow any one channel of the eleven channels to select any register
set to define the respective 2D memory size.

13.4.2.1 W-Size Registers

The W-Size registers (WSRA and WSRB) define the number of bytes that make up the display width. This
allows the DMA controller to calculate the next starting address of another row by adding the
source/destination address to the contents of the W-Size register.
WSRA
WSRB
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
TYPE rw rw rw
0 0 0
RESET
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–16
WS W-Size—Contains the number of bytes that make up the display width.
Bits 15–0
13-16
W-Size Register A
W-Size Register B
28 27 26 25
r r r r
0 0 0 0
12 11 10 9
rw rw rw rw
0 0 0 0
Table 13-11. W-Size Registers Description
MC9328MX1 Reference Manual
24 23 22 21 20
r r r r r
0 0 0 0 0
0x0000
8 7 6 5 4
WS
rw rw rw rw rw
0 0 0 0 0
0x0000
Description
Addr
0x00209040
0x0020904C
19 18 17 16
r r r r
0 0 0 0
3 2 1 0
rw rw rw rw
0 0 0 0
MOTOROLA