Table 30-15 Ssi Transmit Clock Control Register And Ssi Receive Clock Control Register Description - Motorola DragonBall MC9328MX1 Reference Manual

30.3.10 SSI Transmit Clock Control Register and SSI Receive Clock
Control Register
The SSI Transmit Clock Control Register (STCCR) and SSI Receive Clock Control Register (SRCCR)
control the clocks for the SSI. These registers control the prescaler, word length, and frame rate for the
transmit and receive clocks. The fields of this register control the dividers that generate the serial bit clock,
the word clock and the frame clock from the PerCLK3 input. See Section 30.3.10.1, "Calculating the SSI
Bit Clock from the Input Clock Value," for detailed information on clock values.
The STCCR is dedicated to the transmit section, and the SRCCR register is dedicated to the receive section
(except in synchronous mode, when the STCCR controls both the receive and transmit sections). The bit
structure for both registers is identical, however they are two distinct registers and must be individually
programmed.
SSI reset does not affect the STCCR and SRCCR bits. Power-on reset
clears all STCCR and SRCCR bits.
STCCR
SRCCR
BIT 31 30
TYPE r r
0 0
RESET
BIT 15 14
PSR WL
TYPE rw rw
0 0
RESET
Table 30-15. SSI Transmit Clock Control Register and SSI Receive Clock Control Register
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–16
PSR Prescaler Range—Selects whether the fixed divide-by-eight
Bit 15 prescaler will be used to generate the serial bit clock. See Figure 30-4.
Using this prescaler allows a 128 kHz master clock to be generated for
Motorola MC1440x series codecs.
MOTOROLA
NOTE:
SSI Transmit Clock Control Register
SSI Receive Clock Control Register
29 28 27 26 25
r r r r r
0 0 0 0 0
13 12 11 10 9
DC
rw rw rw rw rw
0 0 0 0 0
Description
Description
Synchronous Serial Interface (SSI)
24 23 22 21 20
r r r r
0 0 0 0 0
0x0000
8 7 6 5 4
rw rw rw rw rw
0 0 0 0 0
0x0000
Programming Model
Addr
0x00218014
0x00218018
19 18 17 16
r r r r
0 0 0 0
3 2 1 0
PM
rw rw rw rw
0 0 0 0
Settings
0 = Bypass divide-by-eight
prescaler
1 = Use divide-by-eight
prescaler
30-27
r