Timer Control Registers 1 And 2; Programming Model; Table 26-2 Gp Timers Module Register Memory Map - Motorola DragonBall MC9328MX1 Reference Manual

26.2 Programming Model

The General-Purpose Timers module includes 6 user-accessible 32-bit registers for each timer. Table 26-2
summarizes these registers and their addresses.

26.2.1 Timer Control Registers 1 and 2

Each timer control register (TCTL1 or TCTL2) controls the overall operation of the corresponding
general-purpose timer. Table 26-3 provides the register description. The TCTLx registers control the
following:
• Selecting the free-running or restart mode after a compare event
• Selecting the capture trigger event
• Controlling the output compare mode
• Enabling the compare event interrupt
• Selecting the prescaler clock source
• Enabling and disabling the GP timer
MOTOROLA
Table 26-2. GP Timers Module Register Memory Map
Description
Timer 1 Control Register
Timer 1 Prescaler Register
Timer 1 Compare Register
Timer 1 Capture Register
Timer 1 Counter Register
Timer 1 Status Register
Timer 2 Control Register
Timer 2 Prescaler Register
Timer 2 Compare Register
Timer 2 Capture Register
Timer 2 Counter Register
Timer 2 Status Register
General-Purpose Timers
Name Address
TCTL1 0x00202000
TPRER1 0x00202004
TCMP1 0x00202008
TCR1 0x0020200C
TCN1 0x00202010
TSTAT1 0x00202014
TCTL2 0x00203000
TPRER2 0x00203004
TCMP2 0x00203008
TCR2 0x0020300C
TCN2 0x00203010
TSTAT2 0x00203014
Programming Model
26-3