Basic Mac Operation; Figure 17-1 Mma Data Access - Motorola DragonBall MC9328MX1 Reference Manual

Multimedia Accelerator (MMA)
Figure 17-1 on page 17-2 shows the data access to the eSRAM by the MMA and the ARM920T processor.
AHB Access
Control
DCT
Data Access Controller
17.2.2 MAC
The MAC block provides the MC9328MX1 with fast multiply-accumulate capability. It can perform
1-D × 1-D, 1-D × 2-D, 2-D × 1-D and 2-D × 2-D matrix multiplication to support applications such as
MPEG audio encoder subband filtering, decoder subband synthesis, and MP3 IMDCT.

17.2.2.1 Basic MAC Operation

Two circular data addressing units in the MMA provide the control to fetch data for two operands. All
memory access is in 32–bit words. The MAC can perform 24–bit × 24–bit signed, unsigned, or alternating
sign multiplication. The 48–bit multiplier output is added to a 56–bit accumulator, allowing for 8–bit
overflow. After a user-defined number of MAC iterations, the accumulator value is stored in a 32 × 32–bit
FIFO and the accumulator is cleared. The user can select which 32–bit subset of the 56–bit accumulator
result is stored in the FIFO.
17.2.2.2 Data Access
The two operands for the multiplier are supplied by the X and Y registers. The data for these two registers
is loaded from memory by the data access controller. The MMA maintains two circular buffers in the
eSRAM, one each for the X and Y operands.
To limit how long the bus is held when the MMA accesses memory, the MMA_MAC_BURST register
sets the number of burst cycles permitted for each access, after which the eSRAM is released. The MMA
resumes operation if there are no other eSRAM access requests pending.
Circular buffer operation for the X registers is shown in Figure 17-2 on page 17-3.
17-2
Ctrl Registers
Data Port
MAC
Memory
Controller
eSRAM
Figure 17-1. MMA Data Access
MC9328MX1 Reference Manual
AHB
ARM920T Core
External
Memory
MOTOROLA