Channel Request Time-Out Registers - Motorola DragonBall MC9328MX1 Reference Manual

Table 13-20. Channel Burst Length Registers Description (Continued)
Name
BL Burst Length—Contains the number of data bytes
Bits 5–0 that are transferred in a DMA burst.

13.4.3.7 Channel Request Time-Out Registers

The channel request time-out registers (RTOx) set the time-out for DMA_REQ from the selected request
source of the channel, which detects any discontinuity of data transfer. The request time-out takes effect
only when the corresponding request enable (REN) bit in the channel control register (CCR) is set. An
internal counter starts counting when a DMA channel is enabled, the burst is completed, and the counter is
reset to zero when a DMA request is detected. When the counter reaches the count value set in the register,
it asserts an interrupt and sets its error bit in the DMA request time-out status register. The input clock of
the counter is selectable from either the system clock (HCLK) or input crystal (CLK32K).
This register shares the same address as the bus utilization control register.
RTOR0 Channel 0 Request Time-Out Register
RTOR1 Channel 1 Request Time-Out Register
RTOR2 Channel 2 Request Time-Out Register
RTOR3 Channel 3 Request Time-Out Register
RTOR4 Channel 4 Request Time-Out Register
RTOR5 Channel 5 Request Time-Out Register
RTOR6 Channel 6 Request Time-Out Register
RTOR7 Channel 7 Request Time-Out Register
RTOR8 Channel 8 Request Time-Out Register
RTOR9 Channel 9 Request Time-Out Register
RTOR10 Channel 10 Request Time-Out Register
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
EN CLK PSC
TYPE rw rw rw
0 0 0
RESET
MOTOROLA
Description
NOTE:
28 27 26 25
r r r r
0 0 0 0
12 11 10 9
rw rw rw rw
0 0 0 0
DMA Controller
000000 = 64 bytes read follow 64 bytes write
000001 = 1byte read follow 1 byte write
000010 = 2 bytes read follow 2 bytes write
....
111111 = 63 bytes read follow 63 bytes write
24 23 22 21 20
r r r r r
0 0 0 0 0
0x0000
8 7 6 5 4
CNT
rw rw rw rw rw
0 0 0 0 0
0x0000
Programming Model
Settings
Addr
0x00209098
0x002090D8
0x00209118
0x00209158
0x00209198
0x002091D8
0x00209218
0x00209258
0x00209298
0x002092D8
0x00209318
19 18 17 16
r r r r
0 0 0 0
3 2 1 0
rw rw rw rw
0 0 0 0
13-27