Motorola DragonBall MC9328MX1 Reference Manual page 431

Table 18-6. SPI 1 Control Register and SPI 2 Control Register Description (Continued)
Name
SPIEN SPI Module Enable—Enables/Disables the serial
Bit 9 peripheral interface. SPIEN must be asserted before an
exchange is initiated. Writing 0 to SPIEN flushes the
receive and transmit FIFOs.
XCH Exchange—Initiates a data exchange in master mode.
Bit 8 XCH remains set while the exchange is in progress, or
while the SPI module is waiting for an active SPI_RDY
control signal input. XCH is automatically cleared when
all data in the TXFIFO and shift register are shifted out.
In slave mode, XCH must be cleared.
SSPOL SS Polarity Select—Selects the polarity of the SS
Bit 7 signal (in both master and slave mode).
SSCTL SS Wave Form Select—Selects the output wave form
Bit 6 for the SS signal when in master mode.
Controls RXFIFO advancement when in slave mode for
SPI 1 only.
PHA Phase—Controls the clock/data phase relationship
Bit 5 (see Figure 18-2 on page 18-3).
POL Polarity—Controls the polarity of the SCLK signal (see
Bit 4 Figure 18-2 on page 18-3).
BIT_COUNT Bit Count—Selects the length of the transfer. A
Bits 3–0 maximum of 16 bits can be transferred.
In master mode, a 16-bit data word is loaded from
TXFIFO to the shift register, however only the least n
bits (n=BIT_COUNT) are shifted out. The next 16-bit
word is then loaded to the shift register.
Controls the number of bits in a receive data word (in
slave mode and when the SSCTL bit is 0). When the
SSCTL bit is 1, this field is "don't care."
MOTOROLA
Description
Serial Peripheral Interface Modules (SPI 1 and SPI 2)
Programming Model
Settings
0 = Disable the SPI
1 = Enable the SPI
0 = Idle
1 = Initiates exchange (write) or busy
(read)
0 = Active low
1 = Active high
In master mode:
0 = SS stays low between SPI bursts
1 = Insert pulse between SPI bursts
In slave mode:
0 = RXFIFO advanced by BIT_COUNT
1 = RXFIFO advanced by SS rising edge
0 = Phase 0 operation
1 = Phase 1 operation
0 = Active high polarity (0 = idle)
1 = Active low polarity (1 = idle)
0000 = 1–bit transfer
0001 = 2–bit transfer
...
1111 = 16–bit transfer
18-9