Syncflash Mode Register Programming; Booting From Syncflash; Syncflash Configuration; Figure 24-54 Sync Flash Reset Timing - Motorola DragonBall MC9328MX1 Reference Manual

SDRAM Memory Controller
VCC
SYSTEM
CLOCK
DRAM
RESET
SYSTEM
RESET
RESET_SF
SDCLK
SYNCFLASH
COMMAND

24.9.2 SyncFlash Mode Register Programming

The mode register can be programmed following the initialization sequence, although it is generally not
required. A non-volatile mode register is initially programmed at the same time as the rest of the array.
This non-volatile register is copied into the mode register automatically during device initialization, and
does not require reloading prior to the first operational command. Software may overwrite the default
value at any time the memory is idle using the same sequence as an SDRAM mode register. Consult
Section 24.8.4, "Mode Register Programming," for details.
Programming the SyncFlash non-volatile mode register requires a specialized sequence of load command
register triplets with VccP applied. Consult the SyncFlash data sheet for details.

24.9.3 Booting From SyncFlash

The SDRAM Controller is designed to permit booting from the SyncFlash device immediately out of reset.
Default values in the configuration register allow booting at frequencies up to 100 MHz. Complete
initialization of the controller is still required, however, and must be completed as quickly as possible.

24.9.4 SyncFlash Configuration

Hardware connections are similar to those for SDRAM of like density. One difference is that a SyncFlash
boot device is limited to using CSD1. SyncFlash can be connected to CSD0, however, it cannot be the boot
device. The second difference is the added connection to the reset/powerdown pin (RESET_SF). An
example of a 32-bit configuration is provided in Figure 24-56.
The only significant difference in the software configuration is that refresh must be disabled. SyncFlash
maps the control register access commands to the same basic commands as SDRAM refresh. Enabling
hardware refresh would most likely result in unexpected behavior.
24-66
100 µS Minimum
NOP ACT READ READ
Vector Fetch
Figure 24-54. Sync Flash Reset Timing
MC9328MX1 Reference Manual
Instruction Fetches
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