Motorola DragonBall MC9328MX1 Reference Manual page 30

Figure 17-2 Circular Buffering Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
Figure 17-3 DCT/iDCT Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
Figure 17-4 Data Formatting for DCT and iDCT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
Figure 18-1 SPI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
Figure 18-2 SPI Generic Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
Figure 19-1 LCDC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2
Figure 19-2 LCD Screen Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3
Figure 19-3 Pixel Location on Display Screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4
Figure 19-4 Display Data Mapping, 1/2/4/8 bpp Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5
Figure 19-5 Display Data Mapping, 16 bpp Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7
Figure 19-6 Gray-Scale Pixel Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-8
Figure 19-7 Passive Matrix Color Pixel Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9
Figure 19-8 Active Matrix Color Pixel Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9
Figure 19-9 LCDC Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-11
Figure 19-10 LCDC Interface Timing for 4-bit Data Width Gray-Scale Panels . . . . . . . . . 19-12
Figure 19-11 LCDC Interface Timing for 8-bit Data Passive Matrix Color Panels. . . . . . . 19-13
Figure 19-12 Horizontal Sync Pulse Timing in Passive Mode . . . . . . . . . . . . . . . . . . . . . . 19-14
Figure 19-13 Vertical Sync Pulse Timing Passive, Color, (Non-TFT) Mode . . . . . . . . . . . 19-14
Figure 19-14 LCDC Interface Timing for Active Matrix Color Panels . . . . . . . . . . . . . . . . 19-16
Figure 19-15 Horizontal Sync Pulse Timing in TFT Mode . . . . . . . . . . . . . . . . . . . . . . . . . 19-17
Figure 19-16 Vertical Sync Pulse Timing TFT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-17
Figure 19-17 Register Memory Mapping Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-19
Figure 19-18 Horizontal Timing in MC9328MX1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-31
Figure 20-1 MMC/SD Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2
Figure 20-2 System Interconnection with MMC/SD Module . . . . . . . . . . . . . . . . . . . . . . . 20-2
Figure 20-3 DMAC Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6
Figure 20-4 FIFO Usage for Different Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-8
Figure 20-5 Memory Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-9
Figure 20-6 Card Detection Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-10
Figure 20-7 Block Diagram for Logic and Command Interpreters . . . . . . . . . . . . . . . . . . 20-11
Figure 20-8 Command CRC Shift Register (SD_DAT Has a Similar Structure) . . . . . . . 20-12
Figure 20-9 Clock Tree for the MMC/SD Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-12
Figure 20-10 System Clock Control Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-13
Figure 21-1 Memory Stick Host Controller Simplified Block Diagram . . . . . . . . . . . . . . . 21-2
Figure 21-2 Memory Stick Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3
Figure 21-3 Memory Stick Interrupt Transfer State (BS0) Operation . . . . . . . . . . . . . . . . . 21-6
Figure 21-4 Power Save Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8
Figure 21-5 Auto Command Function Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-10
Figure 21-6 MSHC Module Serial Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11
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