Csi Status Register 1; Table 31-7 Csi Status Register 1 Description - Motorola DragonBall MC9328MX1 Reference Manual

CMOS Sensor Interface Module

31.5.3 CSI Status Register 1

The CSI Status Register 1 (CSISR) contains sensor interface status.
CSISR
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
TYPE r r r
0 0 0
RESET
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–26
SFF_OR_INT STATFIFO Overrun Interrupt—Indicates whether a
Bit 25 STATFIFO overrun is detected. Clear by writing 1.
RFF_OR_INT RxFIFO Overrun Interrupt—Indicates whether an
Bit 24 RxFIFO overrun is detected. Clear by writing 1.
Reserved Reserved—These bits are reserved and should read 0.
Bits 23–22
STATFF_INT STATFIFO Full Interrupt—Indicates whether the
Bit 21 STATFIFO is full. Cleared automatically after a read
from the STATFIFO is performed.
Reserved Reserved—These bits are reserved and should read 0.
Bits 20–19
RXFF_INT RxFIFO Full Interrupt—Indicates whether the
Bit 18 RxFIFO is full. Cleared automatically after a read
from the RxFIFO is performed.
Reserved Reserved—This bit is reserved and should read 0.
Bit 17
SOF_INT Start Of Frame Interrupt—Enables/Disables the
Bit 16 SOF interrupt. When set, SOF interrupt is sampled.
Clear by writing 1.
31-10
CSI Status Register 1
28 27 26 25
SFF_OR RFF_OR
_INT _INT
r r r rw
0 0 0 0
12 11 10 9
r r r r
0 0 0 0
Table 31-7. CSI Status Register 1 Description
Description
MC9328MX1 Reference Manual
24 23 22 21 20
STATFF
_INT
rw r r rw
0 0 0 0
0x0000
8 7 6 5
r r r r
0 0 0 0
0x0000
0 = STATFIFO overrun not detected
1 = STATFIFO overrun detected
0 = RxFIFO overrun not detected
1 = RxFIFO overrun detected
0 = STATFIFO is not full
1 = STATFIFO is full
0 = RxFIFO is not full
1 = RxFIFO is full
0 = Disable SOF interrupt
1 = Enable SOF interrupt
Addr
0x00224008
19 18 17
RXFF_INT SOF_INT
r r rw r
0 0 0 0
4 3 2 1
DRDY
r r r r
0 0 0 0
Settings
MOTOROLA
16
rw
0
0
rw
0