System Clock Controller; Figure 20-8 Command Crc Shift Register (Sd_Dat Has A Similar Structure); Figure 20-9 Clock Tree For The Mmc/Sd Module - Motorola DragonBall MC9328MX1 Reference Manual

Multimedia Card/Secure Digital Host Controller Module (MMC/SD)
CLR_CRC
ZERO
CRC IN CRC
BUS[0]
Figure 20-8. Command CRC Shift Register (SD_DAT Has a Similar Structure)

20.5.4 System Clock Controller

To maximize the power-saving capability of the MMC/SD module, two clock stages are used within. The
input clock, PERCLK2, runs at a frequency between 20–100 MHz and passes through a prescaler to adjust
and maintain the inner clock to under 20 MHz, the maximum operating frequency of the MMC/SD cards.
The output of this prescaler is called CLK_20M. Only about 10% of the total circuit runs on this clock.
CLK_20M feeds into a user-programmable clock divider. The resulting clock is called CLK_DIV and it
runs at a frequency between 0–20 MHz. This clock runs most of the circuitry in the module.
The prescaler and divider ratios are set in the MMC/SD Clock Rate Register (CLK_RATE).
The clocks are paused while they are not used, such as when the FIFO is full during the card read operation
or when there are no further read operations to the FIFO.
IPG_CLK
The system clock controller sets the rate of the MMC/SD module main clock and checks whether it is on or
off. The clock is turned off by setting the STOP_CLK bit in the MMC/SD Clock Control Register
(STR_STP_CLK) and is turned on by setting the START_CLK bit. To change the clock rate, the
application writes new prescaler and divider values in the CLK_RATE register.
20-12
CRC CRC
BUS[1] BUS[2]
CRC OUT
Prescaler
Bus Clock Divider
DMA
Handler
FIFO
DAT
Interrupter
CLK_20M
Transceiver
Figure 20-9. Clock Tree for the MMC/SD Module
MC9328MX1 Reference Manual
CRC CRC
BUS[3] BUS[4]
Inner
Register
Table
Memory
Controller
CMD
Interrupter
CLK_DIV
CRC CRC
BUS[5] BUS[6]
IPS_CLK
MOTOROLA