Motorola DragonBall MC9328MX1 Reference Manual page 953

M
Mapping RAM registers
eight bits/pixel active matrix color mode
register, 19-39
eight bits/pixel passive matrix color mode, 19-38
four bits/pixel active matrix color mode, 19-38
four bits/pixel gray-scale mode, 19-37
four bits/pixel passive matrix color mode, 19-37
one bit/pixel mono mode, 19-37
twelve bits/pixel active matrix color mode, 19-39
MC13180
threshold register
THRESHOLD_I field, 16-57
THRESHOLD_II field, 16-57
threshold register, 16-57
MC9328MX1
-
features of, 1-2 1-11
internal registers, 3-6
introduction, 1-1
MC9328MXL
block diagram, 1-1
MCU PLL and system clock control register 1,
see MPCTL1 register
MCU PLL control register 0, see MPCTL0 register
Memory space
double map image, 3-5
external memory, 3-5
internal register space, 3-5
MCU physical addresses, 3-3
MCU physical memory map, 3-2
memory map description, 3-1
on-chip MCU memory, 3-5
Memory space, 3-1
Memory stick
auto command register, see MSACD register
command register, see MSCMD register
control 2 register, see MSC2 register
control/status register, see MSCS register
DMA request control register,
see MSDRQC register
FIFO access error control/status register,
see MSFAECS register
host controller, see MSHC
parallel port control/data register,
see MSPPCD register
receive FIFO data register, see MSRDATA register
serial clock divider register, see MSCLKD register
transmit FIFO data register,
see MSTDATA register
Memory stick interrupt control/status register
see MSICS register
MOTOROLA
MISCELLANEOUS register
MISCELLANEOUS register, 24-17
MMC/SC
MMC/SD
MMC/SD block length register, see BLK_LEN register
MMC/SD buffer access register,
MMC/SD clock control register, 20-14
MC9328MX1 Reference Manual
OMA bit, 24-17
RMA0 bit, 24-17
program flow operation, 20-33
protection management, 20-45
block read example, 20-40
block read, 20-39
card detection, 20-9
card identification state, 20-33
card internal write protection, 20-45
card registry differences MMC and SD, 20-35
clock control register, 20-14
code example
block write with DMA, 20-38
code listing
card detect, 20-33
send cmd wait response, 20-33
command formats, 20-55
command number register, see CMD register
command types, 20-55
commands and arguments, 20-28
commands and responses, 20-54
commands, 20-56
commands, two types, 20-32
DMA burst request, 20-7
DMA interface, 20-6
features, 20-1
functional description, 20-5
interrupt handling, 20-10
introduction, 20-1
logic/command interpreter, 20-10
mechanical write protect switch, 20-46
memory controller, 20-8
MMC erase, 20-44
password protect, 20-46
pin configuration, 20-5
programming model, 20-13
reset types, 20-34
response formats, 20-60
signal description, 20-5
specific and general commands, 20-55
stream write, 20-42
system clock controller, 20-12
types of cards, 20-3
voltage validation, 20-34
wide bus selection/de-selection, 20-45
write-error detection, 20-8
see BUFFER_ACCESS register
Index-xi