Table 13-22 Channel 0 Bus Utilization Control Registers Description - Motorola DragonBall MC9328MX1 Reference Manual

BUCR0 Channel 0 Bus Utilization Control Register
BUCR1 Channel 1 Bus Utilization Control Register
BUCR2 Channel 2 Bus Utilization Control Register
BUCR3 Channel 3 Bus Utilization Control Register
BUCR4 Channel 4 Bus Utilization Control Register
BUCR5 Channel 5 Bus Utilization Control Register
BUCR6 Channel 6 Bus Utilization Control Register
BUCR7 Channel 7 Bus Utilization Control Register
BUCR8 Channel 8 Bus Utilization Control Register
BUCR9 Channel 9 Bus Utilization Control Register
BUCR10 Channel 10 Bus Utilization Control Register
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
TYPE rw rw rw
0 0 0
RESET
Table 13-22. Channel 0 Bus Utilization Control Registers Description
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–16
CCNT Clock Count—Sets the number of system clocks that must occur before the memory channel
Bits 15–0 releases the AHB, before the next DMA request for the channel.
MOTOROLA
28 27 26 25
r r r r
0 0 0 0
12 11 10 9
rw rw rw rw
0 0 0 0
DMA Controller
24 23 22 21 20
r r r r r
0 0 0 0 0
0x0000
8 7 6 5 4
CCNT
rw rw rw rw rw
0 0 0 0 0
0x0000
Description
Programming Model
Addr
0x00209098
0x002090D8
0x00209118
0x00209158
0x00209198
0x002091D8
0x00209218
0x00209258
0x00209298
0x002092D8
0x00209318
19 18 17 16
r r r r
0 0 0 0
3 2 1 0
rw rw rw rw
0 0 0 0
13-29