Compare Control Register; Table 15-9 Compare Control Register Description - Motorola DragonBall MC9328MX1 Reference Manual

Analog Signal Processor (ASP)
Table 15-8. Pen A/D Sample Rate Control Register Description (Continued)
Name
BIT_SELECT Bit Select—Controls which bits to select from
Bits 11–10 the FIR output.
IDLECNT Idle Count—Controls the number of clocks
Bits 9–4 between the last capture and the first capture
of two pen input points. Input clock to this
counter is fclk.
DSCNT Data Setup Count—Controls the input signal
Bits 3–0 data set up time after the transistor switching
circuit and input select are settled. Input clock
to this counter is fclk.

15.5.3 Compare Control Register

The Compare Control Register is used to detect the out-of-range samples on the selected input. Typical
application of this function is to detect a pen-up event, or to serve as an alarm when the external input is
beyond a specific range.
ASP_CMPCNTL
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
TYPE rw rw rw
0 0 0
RESET
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–20
INT Interrupt Status—Sets when a trigger event is
Bit 19 detected. Write 1 to clear.
15-12
Description
Compare Control Register
28 27 26 25
r r r r
0 0 0 0
12 11 10 9
COMPARE VALUE
rw rw rw rw
0 0 0 0
Table 15-9. Compare Control Register Description
Description
MC9328MX1 Reference Manual
00 = 16 bits starting from 1st MSB of FIR output
01 = 16 bits starting from 2nd MSB of FIR output
10 = 16 bits starting from 3rd MSB of FIR output
11 = 16 bits starting from 4th MSB of FIR output
0x00 = 0 clock
0x01 = 1 clock
...
0x3F = 63 clocks
0000 = 0 clock
0001 = 1 clocks
...
1111 = 15 clocks
24 23 22 21 20
r r r r
0 0 0 0 0
0X0000
8 7 6 5 4
rw rw rw rw rw
0 0 0 0 0
0X0000
0 = No trigger event was detected
1 = A trigger event was detected
Settings
Addr
0x00215030
19 18 17 16
INT CC INSEL
r rw rw rw rw
0 0 0
3 2 1
rw rw rw rw
0 0 0
Settings
MOTOROLA
0
0
0