Csi Rxfifo Register 1; Table 31-9 Csi Module Fifo Register Storage Scheme; Table 31-10 Csi Rxfifo Register 1 Description - Motorola DragonBall MC9328MX1 Reference Manual

CMOS Sensor Interface Module

31.5.5 CSI RxFIFO Register 1

The read-only CSI RxFIFO Register 1 contains received image data. Writing to this register has no effect.
Because the incoming image data is 8-bit and the FIFO size is 32-bit, the incoming data is packed into the
32-bit FIFO in the sequences provided in Table 31-9.
Table 31-9. CSI Module FIFO Register Storage Scheme
FIFO Bits Image Data
31:24 4th byte (LE)
1st byte (BE)
23:16 3rd byte (LE)
2nd byte (BE)
15:8 2nd byte (LE)
3rd byte (BE)
7:0 1st byte (LE)
4th byte (BE)
When a DMA transfer is complete, regardless of big endian or little endian mode, the lowest address in the
RAM always stores the first byte of the incoming data. Likewise, the highest address stores the last byte of
the incoming image data.
CSIRXR
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
TYPE r r r
0 0 0
RESET
Name
IMAGE Image Data—Contains the image data from the CMOS sensor.
Bits 31–0
31-12
Starting Addresses When DMA Transfer is Completed from FIFO to RAM
Stored in highest (Base address + 3) in little endian format
Stored in lowest (Base) address in the big endian format
Stored in Base address + 2 in little endian format
Stored in Base address + 1 in big endian format
Stored in Base address + 1 in little endian format
Stored in Base address + 2 in big endian format
Stored in lowest (Base) address in little endian format
Stored in highest (Base address + 3) in big endian format
CSI RxFIFO Register 1
28 27 26 25
r r r r
0 0 0 0
12 11 10 9
r r r r
0 0 0 0
Table 31-10. CSI RxFIFO Register 1 Description
MC9328MX1 Reference Manual
24 23 22 21 20
IMAGE
r r r r r
0 0 0 0 0
0x0000
8 7 6 5 4
IMAGE
r r r r r
0 0 0 0 0
0x0000
Description
Addr
0x00224010
19 18 17 16
r r r r
0 0 0 0
3 2 1 0
r r r r
0 0 0 0
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