Timer Status Registers 1 And 2; Table 26-8 Timer 1 And 2 Status Registers Description - Motorola DragonBall MC9328MX1 Reference Manual

26.2.6 Timer Status Registers 1 and 2

Each read-only timer status register (TSTAT1 and TSTAT2) indicates the corresponding timer's status.
When a capture event occurs, the CAPT bit is set. When a compare event occurs, the COMP bit is set.
These bits must be cleared to clear the interrupt, if it is enabled. These bits are cleared by writing 0x0 and
will clear only if they have been read while set. This ensures that an interrupt is not missed if it occurs
between the status read and the interrupt clear. The registers and settings are described Table 26-8.
TSTAT1
TSTAT2
BIT 31 30
TYPE r
0
RESET
BIT 15 14
TYPE r
0
RESET
Table 26-8. Timer 1 and 2 Status Registers Description
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–2
CAPT Capture Event—Indicates when a capture event occurs.
Bit 1
COMP Compare Event—Indicates when a compare event occurs.
Bit 0
MOTOROLA
Timer 1 Status Register
Timer 2 Status Register
29 28 27 26
r r r r r
0 0 0 0 0
13 12 11 10
r r r r r
0 0 0 0 0
Description
General-Purpose Timers
25 24 23 22 21
r r r r r
0 0 0 0 0
0x0000
9 8 7 6 5
r r r r r
0 0 0 0 0
0x0000
0 = No capture event occurred
1 = A capture event occurred
0 = No compare event occurred
1 = A compare event occurred
Programming Model
Addr
0x00202014
0x00203014
20 19 18 17
r r r r
0 0 0 0
4 3 2 1
CAPT COMP
r r r r
0 0 0 0
Settings
16
r
0
0
r
0
26-9