Figure 24-1 Sdram Controller Block Diagram - Motorola DragonBall MC9328MX1 Reference Manual

SDRAM Memory Controller
24.2 Block Diagram
Figure 24-1 is a block diagram of the SDRAM Controller.
p_addr p_addr [31:0]
bootmod[1:0]
p_data[31:0]
m_rst m_rst
sd_rst
p_lpmd[1:0]
sd_lpack
p_data[31:0]
24-2
p_addr[25:21]
p_addr[12:9]
Page and Bank
Address
Comparators
Configuration
Registers
Refresh
clk32
Request
Counter
Powerdown
Timer
prefetch
x1clk
bigendian
Figure 24-1. SDRAM Controller Block Diagram
MC9328MX1 Reference Manual
SDBA[4:0]
SDIBA [3:0]
MA11
MA10
MA9
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA0
DQM3
DQM2
DQM1
DQM0
CSD0
CSD1
RAS
CAS
SDWE
SDRAM
Command
SDCKE0
Controller SDCKE1
SDCLK
RESET_SF
sf_wack
Data
Aligner DQ[31:0]
Mux
MC9328MX1
Pins
A[15:11]
A[19:16]
MA11
MA10
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
DQM3
DQM2
DQM1
DQM0
CS2
CS3
RAS
CAS
SDWE
SDCKE0
SDCKE1
SDCLK
RESET_SF
D[31:0]
MOTOROLA