Deep Powerdown Operation With Syncflash; Figure 24-57 Syncflash Clock Suspend Timer Operation Timing Diagram - Motorola DragonBall MC9328MX1 Reference Manual

SDRAM Memory Controller
SDCLK
SDCKEx
64 (CLKST=10) or 128 (CLKST=11) clocks
ADDR
COLUMN
COLUMN
A
t
CL = 2
RAS,
READ
CAS,
SDWE
CSDx
DATA
DATA
A
Figure 24-57. SyncFlash Clock Suspend Timer Operation Timing Diagram
24.9.7 Powerdown Operation with SyncFlash
The SyncFlash enters powerdown mode when the (CLKST [1:0] bits are set to 01 in the SDRAM control
register (SDCTL0/1) and only when no bank is active. In powerdown mode, the clock to the SyncFlash
memory will stop. Again, the powerdown mode can only entered when all banks within the memory area
are inactive. Figure 24-58 illustrates the operation of SyncFlash powerdown mode.
SDCLK
SDCKEx
ADDR
RAS,
CAS,
SDWE
CSDx
DATA
Figure 24-58. SyncFlash Powerdown Operation Timing Diagram

24.10 Deep Powerdown Operation with SyncFlash

The SyncFlash enters deep powerdown mode when the MC9328MX1 enters stop mode (both the MCU
PLL and System PLL are shut down). Upon entry of deep powerdown mode, all active memory banks are
closed, the clock input to the SyncFlash stops, and the RESET_SF signal is asserted. The SyncFlash exits
deep powerdown mode after the MC9328MX1 exits stop mode (when the MCU PLL and System PLL
have waken up) and the clock to the SyncFlash is stable. The RESET_SF signal is then deasserted.
Figure 24-59 illustrates the operation of the SyncFlash when entering deep powerdown mode.
24-70
B
TBST
t
RP (Minimum)
PRE-ALL
MC9328MX1 Reference Manual
COLUMN
B
READ
ROW
ACT
MOTOROLA