Ssi Transmit Configuration Register - Motorola DragonBall MC9328MX1 Reference Manual

Synchronous Serial Interface (SSI)
Table 30-9. I
2
I S Mode
Master or save
Master or save
Master or save
Master or save
Master or save
Master or save
Master or save
Master
Master
Slave
Slave
When the SSI is configured as an I
addition to the sampling rate frequency and bit clock. This oversampling clock is usually required to be
256 times the sampling frequency.
As an example, if a sampling frequency of 44.1 kHz was required, and the word length was set to 16-bits.
Then a frame sync would be 2
The frequency ratios that must hold would be the following:
SYS_CLK (PerCLK3) = 256
Therefore,
If the divide ratio is set to 8—that is, PM = 1 and PSR = 0, SYS_CLK_EN is set, the module is in I
master mode and the incoming frequency of PerCLK3 is 11.2896 MHz, then SYS_CLK will meet the
requirements. The external codec will not need a crystal oscillator for clocking.

30.3.8 SSI Transmit Configuration Register

The SSI Transmit Configuration Register (STCR) controls the transmit operation of the SSI. This register
controls the frame synchronization signal, clocking, and data direction. It also contains enables for the
DMA, transmit FIFO, and the transmit interrupt.
As with all on-chip peripheral interrupts for the MC9328MX1, the STCR must first be set to enable
maskable interrupts. Next, the AITC (ARM9 Interrupt Controller) is configured to handle the SSI
interrupts. For example, the SSI interrupt bits (bits 45 through 42) in the AITC's Interrupt Enable High
30-20
2 2
S Master or I
Bit Register Forced
Name Location Value
RSCKP SRCR [3]
TFSI STCR [2]
RSFI SRCR [2]
TFSL STCR [1]
RFSL SRCR [1]
TEFS STCR [0]
REFS SRCR [0]
TXDIR STCR [5]
TFDIR STCR [6]
TXDIR STCR [5]
TFDIR STCR [6]
2
S master, the external codec may require an oversampling clock in
×
16 = 32 bit clocks. This makes the bit clock frequency 1.4112 MHz.
Frame_Sync = Bit Clock / 32
SYS_CLK (PerCLK3) = 8
MC9328MX1 Reference Manual
S Slave Mode Settings (Continued)
Function
1 Rising edge of bit clock clocks data in
1 Transmit frame sync is active low
1 Receive frame sync is active low
0 Transmit frame sync length is 1 word
0 Receive frame sync length is 1 word
1 Transmit frame sync initiated sync one
bit-clock before transmission
1 Receive frame sync initiated one bit-clock
before receive
1 Clock source is generated internally bit clock
1 Transmit frame sync is generated internally
0 Clock source is externally generated bit clock
0 Transmit frame sync is generated externally
×
Frame Sync
×
Bit Clock
Eqn. 30-1
Eqn. 30-2
Eqn. 30-3
2
S
MOTOROLA