Mode Register Programming Examples; Example 1—256 Mbit Sdram Mode Register; Table 24-40 256 Mbit Sdram Mode Register; Table 24-41 256 Mbit Sdram Mode Register Description - Motorola DragonBall MC9328MX1 Reference Manual

24.8.5 Mode Register Programming Examples

To illustrate how these tables are used and as a demonstration of the programming procedure for the mode
register, two examples are provided. Refer to the SDRAM data sheet for up-to-date characteristics, as the
values used in the example may change from the date of this document's publication.
24.8.5.1 Example 1—256 Mbit SDRAM Mode Register
For Example 1, the following system characteristics will be used:
• 2 Micron MT48LC16M16A2-7E SDRAMs configured as a x32 memory (16M
• 100 MHz system clock frequency
• Non-bank interleaved mode (IAM = 0)
• Burst length of 8 (not optional as the MC9328MX1 performs 8 word burst reads)
• Single word writes (not optional as the MC9328MX1 performs single writes only and does not
provide a burst terminate after each write)
Table 24-40 illustrates the Mode register bit assignments for the Micron 256 Mbit SDRAM.
SDRAM
A12
Address
Mode Register M12
Bit
Content Reserved
Table 24-41. 256 Mbit SDRAM Mode Register Description
Name
WB Write Burst Mode—Needs to be programmed to 1 for
Bit M9 single location accesses.
CAS Latency CAS Latency—Sets latency between column address
Bits M6–M4 and data. Note, the MC9328MX1 does not support CAS
Latencies of 1.
BT Burst Type—Selects sequential or interleaved bursts.
Bit M3
Burst Length Burst Length—A burst length of 8 matches the
Bits M2–M0 ARM920T cache line length.
MOTOROLA
Table 24-40. 256 Mbit SDRAM Mode Register
A11 A10 A9 A8
M11 M10 M9 M8
WB Reserved
Description
SDRAM Memory Controller
A7 A6 A5 A4
M7 M6 M5 M4
CAS latency
0 = Burst writes (not supported by
1 = Single word writes
000 = Reserved
001 = Reserved
010 = 2 clocks
011 = 3 clocks
1xx = Reserved
0 = Sequential
1 = Interleaved
000 = 1
001 = 2
010 = 4
011 = 8
111 = Full page (if BT = 0)
10x = Reserved
1x0 = Reserved
SDRAM Operation
× ×
16 bits 2 chips)
A3 A2 A1 A0
M3 M2 M1 M0
BT Burst length
Settings
MC9328MX1)
24-61