Fifo_Low; Eot—End Of Transfer; Devreq—Device Request; Mdevreq—Multiple Device Request - Motorola DragonBall MC9328MX1 Reference Manual

USB Device Port

28.8.2.5 FIFO_LOW

Each FIFO has an alarm register. The FIFO_LOW interrupt asserts when the byte count in the FIFO is
below the level specified by the alarm register.
28.8.2.6 EOT—End of Transfer
This interrupt asserts after the last data byte of a USB transfer crosses from the USB Core into the UDC
module or vice versa. The end of a USB transfer is indicated by either a zero byte packet or by a data
packet shorter than the maximum packet size for the endpoint.
The EOT never asserts along with the DEVREQ interrupt for setup packets.The EOT interrupt asserts after
every interrupt packet transfer, every complete bulk data transfer and data phase of control transfer. The
EOT interrupt generally asserts along with an EOF interrupt, although an EOT interrupt can occur without
an EOF interrupt when a transfer terminates on a USB packet boundary. The EOT interrupt asserts for
isochronous packet transfers when the UDC module reports that the packet data is error free. This can be
used along with the EOF interrupt to determine when a transfer error of some sort occurs on an
isochronous endpoint.
28.8.2.7 DEVREQ—Device Request
The Device Request (Setup Packet) interrupt means that the most recently received packet was a setup or
device request packet. Software on the USB device must decode and respond to the packet to complete a
Vendor, Class, or Standard request.
28.8.2.8 MDEVREQ—Multiple Device Request
The Multiple Device Requests indicator asserts when two or more setup packets have been received before
the DEVREQ interrupt was cleared. This interrupt is used to determine when the USB host has aborted a
transfer in progress. In this case, the device receives a setup packet, followed by a new setup packet before
it has completed processing of the original command.
28.8.2.9 EOF—End of Frame
This interrupt means that an end-of-frame marker was sent or received on the FIFO/UDC interface. This
interrupt asserts when a DEVREQ is received for bulk, control, isochronous, and interrupt data. While
packet retries are not supported for isochronous endpoints, the end-of-frame indicator is still valid and can
be used along with the SOF interrupt to control data flow.

28.8.3 Interrupts, Missed Interrupts and the USB

Improper operation of the device can result when interrupts are not serviced in a timely manner. For
example, a CFG_CHG interrupt is received, the device does not service it, and another CFG_CHG
interrupt is received. This could leave the device in an incorrect operating mode. The interrupts of concern
in this manner are SOF, CFG_CHG, EOT, and DEVREQ. The missed-interrupt behaviors are discussed in
the following subsections.
28.8.3.1 SOF
When the device misses a start-of-frame interrupt, the MSOF bit asserts in the USB_INTR register.
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