Motorola DragonBall MC9328MX1 Reference Manual page 176

Interrupt Controller (AITC)
Table 10-4. Interrupt Control Register Description (Continued)
Name
NIAD Normal Interrupt Arbiter Disable—Enables/Disables the
Bit 20 assertion of a bus request to the ARM9 core when the normal
interrupt signal (nIRQ) is asserted. When an alternate master
has ownership of the bus when a normal interrupt occurs, the
bus is given back to the ARM9 core after the DMA device has
completed its accesses, so the IRQ_DIS bit does not affect
alternate master accesses that are in progress.
Note: To prevent an alternate master from accessing the
bus during an interrupt service routine, do not clear the
interrupt flag until the end of the service routine.
FIAD Fast Interrupt Arbiter Disable—Enables/Disables the
Bit 19 assertion of a bus request to the ARM9 core when the fast
interrupt signal (nFIQ) is asserted. When an alternate master
has ownership of the bus when a fast interrupt occurs, the
bus is given back to the ARM9 core after the DMA device has
completed its accesses, so the IRQ_DIS bit does not affect
alternate master accesses that are in progress.
Note: To prevent an alternate master from accessing the
bus during an interrupt service routine, do not clear the
interrupt flag until the end of the service routine.
Reserved Reserved—These bits are reserved and should read 0.
Bits 18–0
10-8
Description
MC9328MX1 Reference Manual
Settings
0 = Disregard the normal interrupt
flag when evaluating bus
requests
1 = Normal interrupt flag prevents
alternate masters from
accessing the system bus
0 = Disregard the fast interrupt flag
when evaluating bus requests
1 = Fast interrupt flag prevents
alternate masters from
accessing the system bus
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