Fast Interrupt Vector And Status Register; Table 10-21 Fast Interrupt Vector And Status Register Description - Motorola DragonBall MC9328MX1 Reference Manual

10.4.9 Fast Interrupt Vector and Status Register

The Fast Interrupt Vector and Status Register (FIVECSR) specifies the priority of the highest pending fast
interrupt and provides the vector index for the interrupt's service routine. This hardware mechanism
removes the requirement for ARM920T processor support of the FF1 command. This number can be
directly used as an index into a vector table to select the highest pending fast interrupt source.
This read-only register is located on the ARM920T processor's native bus, is accessible in 1 cycle, and can
be accessed only in supervisor mode. This register must be accessed only on word (32-bit) boundaries.
FIVECSR
BIT 31 30 29
TYPE r r r
1 1 1
RESET
BIT 15 14 13
TYPE r r r
1 1 1
RESET
Table 10-21. Fast Interrupt Vector and Status Register Description
Name
FIVECTOR Fast Interrupt Vector—Indicates vector index
Bits 31–0 for the highest pending fast interrupt.
MOTOROLA
Fast Interrupt Vector and Status Register
28 27 26 25
FIVECTOR [31:16]
r r r r
1 1 1 1
12 11 10 9
FIVECTOR [15:0]
r r r r
1 1 1 1
Description
Interrupt Controller (AITC)
24 23 22 21 20
r r r r
1 1 1 1 1
0xFFFF
8 7 6 5 4
r r r r
1 1 1 1 1
0xFFFF
0 = Interrupt 0 is highest pending fast interrupt
1 = Interrupt 1 is highest pending fast interrupt
...
63 = Interrupt 63 is highest pending fast interrupt
64+ = not used, does not occur
Programming Model
Addr
0x00223044
19 18 17 16
r r r r
1 1 1
3 2 1
r r r r
1 1 1
Settings
10-25
r
1
0
r
1