Clock Source Control Register; Programming Model; Table 12-3 Power Management In The Clock Controller; Table 12-4 Pll And Clock Controller Module Register Memory Map - Motorola DragonBall MC9328MX1 Reference Manual

Table 12-3. Power Management in the Clock Controller
Device/Signal
System PLL When 0 is written to the SPEN bit and the PLL shut-down
count times out (for details see the SD_CNT settings in
Table 12-5 on page 12-6).
MCU PLL When 0 is written to the MPEN bit.
Premultiplier Same as System PLL.
CLK32 Continuously running.

12.5 Programming Model

The PLL and Clock Controller module includes six user-accessible 32-bit registers. Table 12-4
summarizes these registers and their addresses.
Table 12-4. PLL and Clock Controller Module Register Memory Map
MCU PLL and System Clock Control Register 1

12.5.1 Clock Source Control Register

This register controls the various clock sources to the internal modules of the MC9328MX1. It allows the
bypass of the 32 kHz derived clock source to the System PLL when the design requires clock signals with
greater frequency and phase jitter performance than the internal PLL using the 32 kHz clock source
provides.
MOTOROLA
Shut-Down Conditions
Description
Clock Source Control Register
Peripheral Clock Divider Register
MCU PLL Control Register 0
System PLL Control Register 0
System PLL Control Register 1
Phase-Locked Loop and Clock Controller
Programming Model
Wake-Up Conditions
When IRQ or FIQ is asserted.
When IRQ or FIQ is asserted, or 1 is
written to the MPEN bit.
Same as System PLL.
Continuously running.
Name Address
CSCR 0x0021B000
PCDR 0x0021B020
MPCTL0 0x0021B004
MPCTL1 0x0021B008
SPCTL0 0x0021B00C
SPCTL1 0x0021B010
12-5