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Memory Stick Host Controller (MSHC) Module
MSTDATA
BIT
15
14
13
TYPE
w
w
w
0
0
0
RESET
Table 21-9. Memory Stick Transmit FIFO Data Register Description
Name
TX DATA BUFFER
Transmit FIFO Data Buffer—Holds data to transmit. If the buffer is full (MSCS bit TBF=1),
Bits 15–0
the new write data is ignored.
21.7.3 Memory Stick Receive FIFO Data Register
The read-only Memory Stick Receive FIFO Data Register is a 16-bit register. The bit position assignments
for this register are shown in the following register display. The settings for this register are described in
Table 21-10.
This register's value and the FIFO pointers are initialized on power up or when RST bit of Memory Stick
Control/Status Register is 1.
Big/little endian mode of the FIFO DATA register can be set by the LEND bit of the MSC2 register. The
default setting is big-endian. When the LEND bit is 0, the MSHC module handles the FIFO data in
big-endian. In big-endian mode, one data byte incoming via the MS_SDIO pin is received to bits 15
through 8 and next data byte is received to bits 7 through 0 in MSRDATA. Therefore, when only one byte
of data is received from the Memory Stick, the valid data byte is put into bits 15 through 8 in MSRDATA.
When the LEND bit is 1, the MSHC module handles the FIFO data in little-endian. In little-endian mode,
one data byte incoming via the MS_SDIO pin is received to bits 7 through 0 and next byte data is received
to bits 15 through 8 in MSRDATA. Therefore, when only one data byte is received from the Memory
Stick, the valid data byte is put into bits 7 through 0 in MSRDATA.
When RBE is 1, invalid data is read and the FIFO read operation is ignored. The receive FIFO DATA
register must be read only when the MSCS register's DRQ bit or MSICS register's DRQ bit is 1.
MSRDATA
BIT
15
14
13
TYPE
r
r
r
0
0
0
RESET
21-16
Memory Stick Transmit FIFO Data
Register
12
11
10
9
TX DATA BUFFER
w
w
w
w
0
0
0
0
Memory Stick Receive FIFO Data
Register
12
11
10
9
RX DATA BUFFER
r
r
r
r
0
0
0
0
MC9328MX1 Reference Manual
8
7
6
5
4
w
w
w
w
w
0
0
0
0
0
0x0000
Description
8
7
6
5
4
r
r
r
r
r
0
0
0
0
0
0x0000
Addr
0x0021A004
3
2
1
0
w
w
w
w
0
0
0
0
Addr
0x0021A004
3
2
1
0
r
r
r
r
0
0
0
0
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