Motorola DragonBall MC9328MX1 Reference Manual page 947

CSICR1 register
BIG_ENDIAN bit, 31-6
CLR_RXFIFO bit, 31-6
CLR_STATFIFO bit, 31-6
EN bit, 31-7
FCC bit, 31-6
GCLK_MODE bit, 31-7
INV_DATA bit, 31-7
INV_PCLK bit, 31-7
MCLKDIV field, 31-6
MCLKEN bit, 31-6
REDGE bit, 31-7
RF_OR_INTEN bit, 31-5
RXFF_INTEN bit, 31-6
RXFF_LEVEL field, 31-5
SF_OR_INTEN bit, 31-5
SOF_INTEN bit, 31-6
SOF_POL bit, 31-6
STATFF_INTEN bit, 31-5
STATFF_LEVEL field, 31-5
CSICR1 register, 31-5
CSICR2 register
AFS field, 31-8
BTS field, 31-8
DRM bit, 31-8
HSC field, 31-9
LVRM field, 31-9
SCE bit, 31-8
VSC field, 31-9
CSICR2 register, 31-8
CSIRXR register
IMAGE field, 31-12
CSIRXR register, 31-12
CSISR register
DRDY bit, 31-11
RFF_OR_INT bit, 31-10
RXFF_INT bit, 31-10
SFF_OR_INT bit, 31-10
SOF_INT bit, 31-10
STATFF_INT bit, 31-10
CSISR register, 31-10
CSISTATR register
STAT field, 31-11
CSISTATR register, 31-11
CTS
de-assertion, programmable, 27-8
CWT bit, 25-29
CWTEN bit, 25-24
CWTM bit, 25-31
Cyclic redundancy check okay flag, see CRCOK bit
MOTOROLA
D
DARx register
DARx register, 13-20
DATA field, 17-32
Data format control, see IC bit
DATAINSHIFT field, 17-24
DAYALARM register
DAYALARM register, 23-7
DAYR register
DAYR register, 23-4
DBOSR register
DBOSR register, 13-14
DBTOCR register
DBTOCR register, 13-15
DBTOSR register
DBTOSR register, 13-11
DCR register
DCR register, 13-8
DCT ENA bit, 17-25
DCT/IDCT bit, 17-25
DCT_DES_ADDR field, 17-28
DCT_SRC_ADDR field, 17-28
DCTBYPASS bit, 17-24
DCTCLKEN bit, 17-24
DCTCOMP bit, 17-26
DCTXPOSE bit, 17-24
DDIR_A register, 32-9
DDIR_B register, 32-9
DDIR_C register, 32-9
DDIR_D register, 32-9
DDIR_x
DIDEN bit, 17-26
DIIEN bit, 17-26
DIMR register
DININTR bit, 17-27
DISNUM field, 10-11
DISR register, 13-9
DIVISOR field, 25-41
DIVISOR register, 25-41
Divisor register, see DIVISOR register
DMA buffer overflow status register,
MC9328MX1 Reference Manual
DA field, 13-20
DAYSAL field, 23-7
DAYS field, 23-5
bits CH10 through CH0, 13-14
CNT field, 13-15
EN bit, 13-15
bits CH10 through CH0, 13-11
DEN bit, 13-8
DRST bit, 13-8
,
17-27
DDIR field, 32-9
bits CH10 through CH0, 13-10
see DBOSR register
Index-v