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3.2.5.3 Interrupt Mask Register (IMR)
Each bit in the 16-bit IMR corresponds to an INRQ interrupt source. The user masks an in-
terrupt source by clearing the corresponding bit in the IMR. When a masked INRQ interrupt
occurs, the corresponding bit in the IPR is set, but the IMR bit prevents the interrupt request
from reaching the M68000 core. If an INRQ source is requesting interrupt service when the
user clears the IMR bit, the request to the core will cease, but the IPR bit remains set. If the
IMR bit is then set later by the user, the pending interrupt request will once again request
interrupt service and will be processed by the core according to its assigned priority. The
IMR, which can be read by the user at any time, is cleared by reset.
It is not possible to mask the ERR INRQ source in the IMR. Bit 0 of the IMR is undefined.
If a bit in the IMR is masked at the same time that the interrupt
at level 4 is causing the M68000 core to begin the interrupt ac-
knowledge cycle, then the interrupt is not processed, and one of
two possible cases will occur. First, if other unmasked interrupts
are pending at level 4, then the interrupt controller will acknowl-
edge the interrupt with a vector from the next highest priority un-
masked interrupt source. Second, if no other interrupts are
pending at level 4, then the interrupt controller will acknowledge
the interrupt with the error vector (00000 binary).
To avoid handling the error vector, the user can raise the inter-
rupt mask in the M68000 core status register (SR) to 4 before
masking the interrupt source and then lower the level back to its
original value. Also, if the interrupt source has multiple events
(e.g., SCC1), then the interrupts for that peripheral can be
masked within the peripheral mask register.
To clear bits that were set by multiple interrupt events, the user
should clear all the unmasked events in the corresponding on-
chip peripheral's event register.
15
14
PB11
PB10
7
6
PB9
TIMER2
MOTOROLA
NOTE
NOTE
13
12
SCC1
SDMA
5
4
SCP
TIMER3
MC68302 USER'S MANUAL
System Integration Block (SIB)
11
10
IDMA
SCC2
3
2
SMC1
SMC2
9
8
TIMER1
SCC3
1
0
PB8
—
3-27
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