Table of Contents
Advertisement
Chapter 21
Memory Stick Host Controller (MSHC) Module
21.1 Overview
This chapter describes how data is transferred to a Memory Stick device and discusses how to configure
and program the Memory Stick Host Controller (MSHC) module.
21.2 Features
The MSHC module provides the following features:
•
Integrated 8-byte (4-half-word) FIFO buffers for transmit and receive
•
Integrated CRC circuit
•
Host bus clock supports HCLK maximum setting (96 MHz)
•
DMA support with selectable DMA request condition based on FIFO status
•
Automatic command execution (can be toggled on/off) when an interrupt from the Memory Stick
is detected
•
Built-in Serial Clock Divider: maximum 25 MHz serial data transfer rate
•
Protocol is started by writing to the Memory Stick Command Register from the ARM920T core
•
Data is requested by DMA or interrupt requests to the ARM920T core on entering the data period
•
RDY time-out period can be set by the number of serial clock cycles
•
Interrupt can be output to the ARM920T core when a time-out occurs
•
CRC can be turned off during test mode
•
Two integrated general purpose input ports
•
16-bit host bus access (byte access not supported)
21.3 Block Diagram and Description
Figure 21-1 on page 21-2 shows a high-level block diagram of the MSHC module.
MOTOROLA
Memory Stick Host Controller (MSHC) Module
21-1
Advertisement
Chapters
Table of Contents
