Mmc/Sd Clock Rate Register; Table 20-7 Mmc/Sd Clock Rate Register Description - Motorola DragonBall MC9328MX1 Reference Manual

20.6.3 MMC/SD Clock Rate Register

The MMC/SD Clock Rate Register defines the clock divider values for CLK_20M and CLK_DIV. These
two signals are used to clock the MMC/SD module. See Section 20.5.4, "System Clock Controller," for
more information on clock schemes.
The user can write to the MMC/SD Clock Rate Register only when the bus
clock is stopped. Check the CARD_BUS_CLK_RUN bit of the STATUS
register to determine the state of the bus clock.
CLK_RATE
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
TYPE r r r
0 0 0
RESET
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–6
PRESCALER Prescaler Divider—Specifies the divider value to generate
Bits 5–3 CLK_20M. PERCLK2 feeds into the MMC/SD module from
the clock controller.
CLK RATE Inner Bus Clock Divider—Specifies the divider value to
Bits 2–0 generate CLK_DIV. The CLK_20M signal feeds into the
inner bus clock divider from the prescaler.
MOTOROLA Multimedia Card/Secure Digital Host Controller Module (MMC/SD)
MMC/SD Clock Rate Register
28 27 26 25
r r r r
0 0 0 0
12 11 10 9
r r r r
0 0 0 0
Table 20-7. MMC/SD Clock Rate Register Description
Description
NOTE:
24 23 22 21
r r r r
0 0 0 0
0x0000
8 7 6 5
PRESCALER
r r r rw
0 0 0 1
0x0036
000 = CLK_20M is PERCLK2
001 = CLK_20M is PERCLK2 ÷ 2
010 = CLK_20M is PERCLK2 ÷ 3
011 = CLK_20M is PERCLK2 ÷ 3
100 = CLK_20M is PERCLK2 ÷ 4
101 = CLK_20M is PERCLK2 ÷ 5
110 = CLK_20M is PERCLK2 ÷ 5
111 = CLK_20M is PERCLK2 ÷ 5
000 = CLK_DIV is CLK_20M
001 = CLK_DIV is CLK_20M ÷ 2
010 = CLK_DIV is CLK_20M ÷ 4
011 = CLK_DIV is CLK_20M ÷ 8
100 = CLK_DIV is CLK_20M ÷ 16
101 = CLK_DIV is CLK_20M ÷ 32
110 = CLK_DIV is CLK_20M ÷ 64
111 = CLK_DIV is CLK_20M ÷ 64
Programming Model
Addr
0x00214008
20 19 18 17
r r r r
0 0 0 0
4 3 2 1
CLK RATE
rw rw rw rw
1 0 1 1
Settings
20-19
16
r
0
0
rw
0