Table 27-3 Interrupts And Dma - Motorola DragonBall MC9328MX1 Reference Manual

Universal Asynchronous Receiver/Transmitters (UART) Modules
Pin
UART2_CTS Primary function of
GPIO Port B [28]
UART2_DSR Alternate function
of GPIO Port D [10]
UART2_RI Alternate function
of GPIO Port D [9]
UART2_DCD Alternate function
of GPIO Port D [8]
UART2_DTR Alternate function
of GPIO Port D [7]
27.3 Interrupts and DMA Requests
Table 27-3 lists all of the interrupts that are output on each interrupt output. See the individual register
descriptions for explanation of available enables and status flags.
Interrupt Output
UART_MINT_DTR
UART_MINT_RTS
UART_MINT_RX
UART_MINT_TX
UART_MINT_UARTC
UART_MINT_PFRERR
UART_RX_DMAREQ
27-4
Table 27-2. Pin Configuration (Continued)
Setting
1.Clear bit 28 of Port B GPIO In Use Register (GIUS_B)
2.Clear bit 28 of Port B General Purpose Register (GPR_B)
1.Clear bit 10 of Port D GPIO In Use Register (GIUS_D)
2.Set bit 10 of Port D General Purpose Register (GPR_D)
1.Clear bit 9 of Port D GPIO In Use Register (GIUS_D)
2.Set bit 9 of Port D General Purpose Register (GPR_D)
1.Clear bit 8 of Port D GPIO In Use Register (GIUS_D)
2.Set bit 8 of Port D General Purpose Register (GPR_D)
1.Set bit 7 of Port D GPIO In Use Register (GIUS_D)
2.Set bit 7 of Port D General Purpose Register (GPR_D)
Table 27-3. Interrupts and DMA
Interrupt Enable Register
Enable Location
DTREN UCR3_2 (bit 13)
RTSDEN UCR1_1/UCR1_2 (bit 5)
RTSEN UCR2_1/UCR2_2 (bit 4)
RRDYEN UCR1_1/UCR1_2 (bit 9)
IDEN UCR1_1/UCR1_2 (bit 12)
DREN UCR4_1/UCR4_2 (bit 0)
RXDSEN UCR3_1/UCR3_2 (bit 6)
TXMPTYEN UCR1_1/UCR1_2 (bit 6)
TRDYEN UCR1_1/UCR1_2 (bit 13)
TCEN UCR4_1/UCR4_2 (bit 3)
OREN UCR4_1/UCR4_2 (bit 1)
BKEN UCR4_1/UCR4_2 (bit 2)
WKEN UCR4_1/UCR4_2 (bit 7)
ADEN UCR1_1/UCR1_2 (bit 15)
ESCI UCR2_1/UCR2_2 (bit 15)
ENIRI UCR4_1/UCR4_2 (bit 8)
AIRINTEN UCR3_1/UCR3_2 (bit 5)
AWAKEN UCR3_1/UCR3_2 (bit 4)
FRAERREN UCR3_1/UCR3_2 (bit 11)
PARERREN UCR3_1/UCR3_2 (bit 12)
RDMAEN UCR1_1/UCR1_2 (bit 8)
MC9328MX1 Reference Manual
Configuration Procedure
Interrupt
Flag
DTRF USR2_2 (bit 13)
RTSD USR1_1/USR1_2 (bit 12)
RTSF USR2_1/USR2_2 (bit 4)
RRDY USR1_1/USR1_2 (bit 9)
IDLE USR2_1/USR2_2 (bit 12)
RDR USR2_1/USR2_2 (bit 0)
RXDS USR1_1/USR1_2 (bit 6)
TXFE USR2_1/USR2_2 (bit 14)
TRDY USR1_1/USR1_2 (bit 13)
TXDC USR2_1/USR2_2 (bit 3)
ORE USR2_1/USR2_2 (bit 1)
BRCD USR2_1/USR2_2 (bit 2)
WAKE USR2_1/USR2_2 (bit 7)
ADET USR2_1/USR2_2 (bit 15)
ESCF USR1_1/USR1_2 (bit 11)
IRINT USR2_1/USR2_2 (bit 8)
AIRINT USR1_1/USR1_2 (bit 5)
AWAKE USR1_1/USR1_2 (bit 4)
FRAERR USR1_1/USR1_2 (bit 10)
PARITYERR USR1_1/USR1_2 (bit 15)
RRDY USR1_1/USR1_2 (bit 9)
Flag Register
Location
MOTOROLA