Interrupt Mask Registers; Table 32-17 Interrupt Mask Register Description - Motorola DragonBall MC9328MX1 Reference Manual

Integrated portable system processor
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32.5.8 Interrupt Mask Registers

The Interrupt Mask Registers determine whether an interrupt is active. When an interrupt event occurs and
the bit in this register is set (active), then the corresponding bit in the Interrupt Status Register (ISR) is set.
There are four distinct Interrupt Mask Registers; each holds the data for one of the four GPIO ports (Port
A, Port B, Port C, and Port D).
IMR_A
IMR_B
IMR_C
IMR_D
BIT
31
30
29
TYPE
rw
rw
rw
0
0
0
RESET
BIT
15
14
13
TYPE
rw
rw
rw
0
0
0
RESET
Name
IMR [i]
Interrupt Mask—Masks the interrupts for this module.
Bits 31–0
MOTOROLA
Port A Interrupt Mask Register
Port B Interrupt Mask Register
Port C Interrupt Mask Register
Port D Interrupt Mask Register
28
27
26
25
rw
rw
rw
rw
0
0
0
0
12
11
10
9
rw
rw
rw
rw
0
0
0
0
Table 32-17. Interrupt Mask Register Description
Description
GPIO Module and I/O Multiplexer (IOMUX)
24
23
22
21
20
IMR
rw
rw
rw
rw
rw
0
0
0
0
0
0x0000
8
7
6
5
4
IMR
rw
rw
rw
rw
rw
0
0
0
0
0
0x0000
Programming Model
Addr
0x0021C030
0x0021C130
0x0021C230
0x0021C330
19
18
17
16
rw
rw
rw
rw
0
0
0
0
3
2
1
0
rw
rw
rw
rw
0
0
0
0
Settings
0 = Interrupt is masked
1 = Interrupt is not masked
32-21

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