Interrupt Mask Register (Imr); Interrupt In-Service Register (Isr) - Motorola MC68302 User Manual

NOTE
The ERR bit is set if the user drives the IPL2-IPLO lines to interrupt
level 4 and no INRQ interrupt is pending.
15 14 13 12 11 10 9 8 7 6 5 4 3 2
I
PBl 1
I
PB10
I
SCCl
I
SOMA
I
JOMA
I
SCC2
I
TIMER!
I
SCC3
I
PBS
I
TIMER2
j
SCP
I
TIMER3
I
SMC!
I
SMC2
I
PBS ERR
3.2.5.3 INTERRUPT MASK REGISTER (IMR). Each bit in the 16-bit IMR corresponds
to an INRQ interrupt source. The user masks an interrupt source by clearing
the corresponding bit in the IMR. When a masked INRQ interrupt occurs, the
corresponding bit in the IPR is set, but the IMR bit prevents the interrupt
request from reaching the M68000 core. If an INRQ source is requesting
interrupt service when the user clears the IMR bit, the request to the core
will cease, but the IPR bit remains set. If the IMR bit is then set later by the
user, the pending interrupt request will once again request interrupt service
and will be processed by the core according to its assigned priority. The IMR,
which can be read by the user at any time, is cleared by reset.
NOTE
To clear bits that were set by multiple interrupt events, the user
should clear all the unmasked events in the corresponding on-chip
peripheral's event register.
15 14 13 12 11 10 9 B 7 6 5 4 3 2 0
I
PBl 1
I
PB10
I
SCCl
I
SOMA
I
10MA
I
SCC2
I
TIMER!
I
SCC3
I
PB9
I
TIMER2
I
SCP
I
TIMER3
I
SMC!
I
SMC2
I
PBB ERR
I
3.2.5.4 INTERRUPT IN-SERVICE REGISTER (ISR). Each bit in the 16-bit ISR cor-
responds to an INRQ interrupt source. In a vectored interrupt environment,
the interrupt controller sets the ISR bit when the vector number correspond-
acknowledge cycle. The user's interrupt service routine should clear this bit
during the servicing of the interrupt. To clear a bit in the ISR, the user writes
a one to that bit. Since the user can only clear bits in this register, the bits
that are written as zeros will not be affected. The ISR is cleared by reset.
This register may be read by the user to determine which INRQ interrupts
are currently being processed. More than one bit in the ISR may be a one if
the capability is used to allow higher priority level 4 interrupts to interrupt
lower priority level 4 interrupts. See 3.2.2.3 NESTED INTERRUPTS for more
details.
MOTOROLA MC68302 USER'S MANUAL
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