Native Clock Low Register; Table 16-19 Native Clock Low Register Description - Motorola DragonBall MC9328MX1 Reference Manual

Bluetooth Accelerator (BTA)

16.5.2.4 Native Clock Low Register

The Native Clock Low Register concatenated with the Native Clock High Register (see section 16.5.2.5)
comprise the free-running Bluetooth NATIVECLK. The Native Clock Low Register contains the 16 least
significant bits (LSB) of the 28-bit NATIVECLK.
Writing to the Offset Clock Low Register and the Offset Clock High Register updates ESTIMATEDCLK
with the sum of NATIVECLK and OFFSETCLK on the next NATIVECLK tick.
The Native Clock Low Register bits are described in Table 16-19.
NATIVECLK_LOW
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
TYPE rw rw rw
0 0 0
RESET
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–16
NATIVECLK_LOW Lower Two Bytes of the NATIVECLK—Contains the LSB (bits 15–0) of the 28-bit
Bits 15–0 NATIVECLK.
16-34
Native Clock Low Register
28 27 26 25
r r r r
0 0 0 0
12 11 10 9
rw rw rw rw
0 0 0 0
Table 16-19. Native Clock Low Register Description
MC9328MX1 Reference Manual
24 23 22 21
r r r r
0 0 0 0
0x0000
8 7 6 5
NATIVECLK_LOW
rw rw rw rw
0 0 0 0
0x0000
Description
Addr
0x00216018
20 19 18 17
r r r r
0 0 0 0
4 3 2 1
rw rw rw rw
0 0 0 0
MOTOROLA
16
r
0
0
rw
0