Table 10-2 Aitc Module Register Memory Map; Programming Model - Motorola DragonBall MC9328MX1 Reference Manual

Interrupt Controller (AITC)
Bit #
18
19
20
21
22
23
24
25
26
27
28
29
30
31

10.4 Programming Model

The AITC module includes 26 user-accessible 32-bit registers. All of these registers are single cycle access
because the AITC sits on the native bus of the ARM920T processor. Table 10-2 summarizes these registers
and their addresses. Table 10-3 provides an overview of the register fields.
Normal Interrupt Mask Register
Interrupt Enable Number Register
Interrupt Disable Number Register
Normal Interrupt Priority Level Register 7
10-4
Table 10-1. Interrupt Assignment (Continued)
Name of Interrupt
RTC_SAM_INT
UART2_MINT_PFERR
UART2_MINT_RTS
UART2_MINT_DTR
UART2_MINT_UARTC
UART2_MINT_TX
UART2_MINT_RX
UART1_MINT_PFERR
UART1_MINT_RTS
UART1_MINT_DTR
UART1_MINT_UARTC
UART1_MINT_TX
UART1_MINT_RX
Unused
Table 10-2. AITC Module Register Memory Map
Description
Interrupt Control Register
Interrupt Enable Register High
Interrupt Enable Register Low
Interrupt Type Register High
Interrupt Type Register Low
MC9328MX1 Reference Manual
Bit # Name of Interrupt
50 USBD_INT [3]
51 USBD_INT [4]
52 USBD_INT [5]
53 USBD_INT [6]
54 Unused
55 BTSYS
56 BTTIM
57 BTWUI
58 TIMER2_INT
59 TIMER1_INT
60 DMA_ERR
61 DMA_INT
62 GPIO_INT_PORTD
63 WDT_INT
Name Address
INTCNTL 0x00223000
NIMASK 0x00223004
INTENNUM 0x00223008
INTDISNUM 0x0022300C
INTENABLEH 0x00223010
INTENABLEL 0x00223014
INTTYPEH 0x00223018
INTTYPEL 0x0022301C
NIPRIORITY7 0x00223020
MOTOROLA