Mma Mac Fifo Status Register; Table 17-9 Mma Mac Fifo Status Register Description - Motorola DragonBall MC9328MX1 Reference Manual

Integrated portable system processor
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17.3.1.8 MMA MAC FIFO Status Register

MMA_MAC_FIFO_ST
AT
BIT
31
30
TYPE
r
r
0
0
RESET
BIT
15
14
TYPE
r
r
0
0
RESET
Table 17-9. MMA MAC FIFO Status Register Description
Name
Reserved
Reserved—These bits are reserved and should read 0.
Bits 31–21
FIFO COUNT
FIFO Data Count—Indicates the number of data in the FIFO.
Bits 20–16
Reserved
Reserved—These bits are reserved and should read 0.
Bits 15–3
FIFO EMPT
FIFO Empty Status—Indicates the status of the FIFO EMPT
Bit 2
interrupt.
FIFO HALF
FIFO Half Full Status—Indicates the status of the FIFO HALF
Bit 1
interrupt.
FIFO FULL
FIFO Full Status—Indicates the status of the FIFO FULL interrupt.
Bit 0
MOTOROLA
MMA MAC FIFO Status Register
29
28
27
26
25
r
r
r
r
r
0
0
0
0
0
13
12
11
10
9
r
r
r
r
r
0
0
0
0
0
Description
Multimedia Accelerator (MMA)
24
23
22
21
20
r
r
r
r
r
0
0
0
0
0
0x0000
8
7
6
5
4
r
r
r
r
r
0
0
0
0
0
0x0004
Programming Model
Addr
0x0022201C
19
18
17
16
FIFO COUNT
r
r
r
r
0
0
0
0
3
2
1
0
FIFO
FIFO
FIFO
EMPT
HALF
FULL
r
r
r
r
0
1
0
0
Settings
See description
See description
See description
See description
17-13

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