Estimated Clock Low Register; Table 16-21 Estimated Clock Low Register Description - Motorola DragonBall MC9328MX1 Reference Manual

Bluetooth Accelerator (BTA)

16.5.2.6 Estimated Clock Low Register

The Estimated Clock Low Register concatenated with the Estimated Clock High Register (see section
16.5.2.7) comprise the estimated Bluetooth clock. The Estimated Clock Low Register contains the 16 least
significant bits (LSB) of the 28-bit ESTIMATEDCLK. The Estimated Clock Low Register bits are
described in Table 16-21.
ESTIMATED_CLK_LOW
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
TYPE rw rw rw
0 0 0
RESET
Table 16-21. Estimated Clock Low Register Description
Name
Reserved
Bits 31–16
ESTIMATED_CLK_LOW
Bits 15–0
16-36
Estimated Clock Low Register
28 27 26 25
r r r r
0 0 0 0
12 11 10 9
ESTIMATED_CLK_LOW
rw rw rw rw
0 0 0 0
Reserved—These bits are reserved and should read 0.
Lower 2 Bytes of the ESTIMATEDCLK—Contains the LSB (bits 15–0) of the 28-bit
ESTIMATEDCLK.
MC9328MX1 Reference Manual
24 23 22 21 20
r r r r r
0 0 0 0 0
0x0000
8 7 6 5 4
rw rw rw rw rw
0 0 0 0 0
0x0005
Description
Addr
0x00216020
19 18 17 16
r r r r
0 0 0 0
3 2 1 0
rw rw rw rw
0 1 0 1
Settings
MOTOROLA