Global Clock Control Register; Table 8-5 Global Clock Control Register Description - Motorola DragonBall MC9328MX1 Reference Manual

System Control

8.1.4 Global Clock Control Register

The Global Clock Control Register (GCCR) provides additional power saving capabilities by controlling
the clocks in the following MC9328MX1 modules: DMA, CSI, MMA and USB. It also controls the clock
source for Bootstrap mode.
GCCR
BIT 31 30 29 28
TYPE r r r
0 0 0
RESET
BIT 15 14 13 12
TYPE r r r
0 0 0
RESET
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–5
BROM_ BROM Clock Enable—Only available in Bootstrap
CLK_EN mode. This bit enables/disables the operational
Bit 4 system boot mode of the MC9328MX1 upon system
reset. The boot mode is determined by the settings of
these pins.
DMA_ DMA Clock Enable—Enables/Disables clock input to
CLK_EN the DMA module.
Bit 3
CSI_ CMOS Sensor Interface Clock Enable—
CLK_EN Enables/Disables clock input to the CSI module.
Bit 2
MMA_ Multimedia Accelerator Clock Enable—
CLK_EN Enables/Disables clock input to the MMA module.
Bit 2
USBD_ USBD Clock Enable—Enables/Disables clock input
CLK_EN to the USB module.
Bit 2
8-6
Global Clock Control Register
27 26 25 24
r r r r r
0 0 0 0 0
11 10 9 8
r r r r r
0 0 0 0 0
Table 8-5. Global Clock Control Register Description
Description
MC9328MX1 Reference Manual
23 22 21 20
r r r r
0 0 0 0
0x0000
7 6 5 4
BROM_
CLK_EN CLK_EN
r r r rw
0 0 0 0
0x000F
0 = Clock gating is controlled by setting of
BOOT[3:0] pins.
1 = Overrides the setting of the BOOT[3:0]
pins and forces the HCLK to be used as
clock.
0 = DMA clock input is disabled.
1 = DMA clock input is enabled (default).
0 = CSI clock input is disabled.
1 = CSI clock input is enabled (default).
0 = CSI clock input is disabled.
1 = CSI clock input is enabled (default).
0 = USB clock input is disabled.
1 = USB clock input is enabled (default).
0x0021B810
19 18 17
r r r
0 0 0
3 2 1
DMA_ CSI_ MMA_
CLK_EN CLK_EN
rw rw rw
1 1 1
Settings
MOTOROLA
Addr
16
r
0
0
USBD_
CLK_EN
rw
1