Dct/Idct Data Fifo; Table 17-34 Dct/Idct Data Fifo Register Description - Motorola DragonBall MC9328MX1 Reference Manual

Multimedia Accelerator (MMA)

17.3.5.11 DCT/iDCT Data FIFO

MMA_DCTFIFO
BIT 31 30 29
TYPE rw rw rw
0 0 0
RESET
BIT 15 14 13
TYPE rw rw rw
0 0 0
RESET
Table 17-34. DCT/iDCT Data FIFO Register Description
Name
DATA Data—Stores input data to be transformed and the outputs the data after transformation. Writing to
Bits 31–0 this register stores input data in the FIFO. Reading this register retrieves the results of the
transformation from the FIFO. The FIFO is 32 × 32–bits.
17-32
DCT/iDCT Data FIFO
28 27 26 25
rw rw rw rw
0 0 0 0
12 11 10 9
rw rw rw rw
0 0 0 0
MC9328MX1 Reference Manual
24 23 22 21 20
DATA
rw rw rw rw rw
0 0 0 0 0
0x0000
8 7 6 5 4
DATA
rw rw rw rw rw
0 0 0 0 0
0x0000
Description
Addr
0x00222500
19 18 17 16
rw rw rw rw
0 0 0 0
3 2 1 0
rw rw rw rw
0 0 0 0
MOTOROLA