Motorola DragonBall MC9328MX1 Reference Manual page 433

Table 18-7. SPI 1 Interrupt Control/Status Register and
SPI 2 Interrupt Control/Status Register Description (Continued)
Name
BO Bit Count Overflow—Indicates that a bit count overflow has
Bit 7 occurred. BO is applicable for the SPI 1 module only when the
bits of CONTROLREG1 are set so that
MODE = 0 and SSCTL = 1. The overflow occurs when the
slave receives more than 16 bits in one burst. BO is cleared
after a data read from the RXDATAREG1 register. There is no
way to determine which data word overflowed, so the bad
data word can still be in the FIFO if it is not empty.
RO RXFIFO Overflow—Indicates that the RXFIFO has
Bit 6 overflowed. At least one newly written data word has been
lost. The RO flag is automatically cleared after a data read.
RF RXFIFO Full Status—Indicates that the RXFIFO is full.
Bit 5
RH RXFIFO Half Status—Indicates that the RXFIFO is at least
Bit 4 half-full.
RR RXFIFO Data Ready Status—Indicates that the RXFIFO is
Bit 3 empty.
TF TXFIFO Full Status—Indicates that the TXFIFO is full.
Bit 2
TH TXFIFO Half Status—Indicates that the TXFIFO is at least
Bit 1 half-empty.
TE TXFIFO Empty Status—Indicates that the TXFIFO is empty.
Bit 0
MOTOROLA
Description
Serial Peripheral Interface Modules (SPI 1 and SPI 2)
Programming Model
Settings
0 = No bit count overflow error
1 = At least one data word in
RXFIFO has a bit count
overflow error
0 = No RXFIFO overflow error
1 = At least one data word in the
RXFIFO has been overwritten
0 = Less than 8 data words are in
the RXFIFO
1 = 8 data words are in the RXFIFO
0 = Less than 4 data words are in
the RXFIFO
1 = At least 4 data words are in the
RXFIFO
0 = The RXFIFO is empty
1 = At least one data word is in the
RXFIFO
0 = Less than 8 data words are in
the TXFIFO
1 = 8 data words are in the TXFIFO
0 = Less than 4 empty slots are in
the TXFIFO
1 = At least 4 empty slots are in the
TXFIFO
0 = At least one data word is in the
TXFIFO
1 = The TXFIFO is empty, however
data shifting may still be
on-going. To be sure no data
transaction is on-going, check
the XCH bit(s) in the Control
Register(s).
18-11