Figure 21-13 Signal Timing; Table 21-24 Two State Access Mode Factor - Motorola DragonBall MC9328MX1 Reference Manual

Memory Stick Host Controller (MSHC) Module
21.8.4.2 Two State Access Mode Factor
Error
TPC Code Error 4 Bit Error Check
Code Error
Undefined TPC
Unacceptable TPC
Short TPC State
Data Error Write Packet CRC
Error
Short Data State
Handshake Error Short Handshake
State
Power Supply On —
When no error occurs in BS1, the bus state shifts to BS2, BS3 and enters Four State Access Mode. When
an error described above occurs, it returns to Two State Access Mode again.
21.8.5 Signal Timing
21.8.5.1 Timing
• Timing of SCLK, SDIO and BS
— Sender outputs SDIO signal at SCLK fall (output side), and latches it at SCLK rise (input side).
• BS signal is output synchronizing with SCLK fall
21-30
Table 21-24. Two State Access Mode Factor
—
—
TPC is received, however the Memory Stick is not capable of
executing it due to internal status.
When BS1 is under 8 SCLKO.
CRC error occurred in the data transferred from MSHC module.
Not all data are accepted because data state of BS is shorter than the
setting on Memory Stick.
BS is switched before the output of RDY, though Memory Stick is
operating normally.
—
BS
SDIO
D2 D1
SCLK
1 Change timing of BS
2 Timing to detect BS change on Memory Stick side
1 Timing to output LSB of final data
2
Timing to latch LSB of final data
3
Timing to output MSB of first data
4 Timing to latch MSB of first data
Figure 21-13. Signal Timing
MC9328MX1 Reference Manual
Description
D0 D7 D6
1 3
2 4
MOTOROLA