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14.6 Watchdog Timer I/O Signals
Table 14-1shows the watchdog timer module input and output signals.
Signal Name
FIQ
IRQ
IPS_HARD_ASYNC_RESET
IPS_CONT_CLK
IPS_CONT_CLK
IPS_GATED_CLK
IPS_GATED_CLK
CLK2HZ
CLK32K
IPS_MODULE_EN
IPS_BYTE_15_8
IPS_BYTE_7_0
IPS_MRW
IPS_ADDR[11:2]
IPS_WDATA[31:0]
SCAN_MODE
SCAN_RESET
IPS_CONT_CLK_EN
IPS_XFR_ERR
IPS_XFR_WAIT
IPS_RDATA[31:0]
MOTOROLA
Table 14-1. Watchdog Timer I/O Signals
I/O
I
Fast Interrupt
I
Normal Interrupt
I
WDOG global reset from reset module
I
96 MHz system clock
I
96 MHz system clock inverted
I
Bus clock
I
Bus clock inverted
I
2 Hz clock input from RTC module output
I
in test mode, counter clock becomes 32 kHz clock
I
Watchdog module enable
I
Bit 15 to 8 enable
I
Bit 7 to 0 enable
I
Module read/write signal
I
Module address bus
I
Module write data bus
I
Indicates scan mode selection
I
Indicates scan reset
O
ips_cont_clk enable
O
Transfer error acknowledge
O
Transfer wait acknowledge
O
Module read data bus
Watchdog Timer Module
Watchdog Timer I/O Signals
Description
14-5
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