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Index Register
Address Index added to the
Base Register to yield the
actual physical location
a) Initially
+
b) After every
MMA_MAC_XCOUNT
iteration if the
X INDEX LOAD bit is set.
Increment Register
This value is added to the
Index Register after every
XCOUNT iteration if the
X INDEX INCR bit is set.
17.2.2.3 Cache
The X operand access has an associated cache and cache controller. Initially, the cache is cleared and the X
operand data is accessed from the eSRAM and stored in the cache. Subsequent accesses to the same
address cause a cache hit and the data is accessed from the cache.
The cache is a memory block of 512 24–bit words. Each word also has an associated valid bit to indicate
data validity. The cache can be enabled or disabled. To fully use the cache, the base address of the operand
must be on a 2K boundary. When a data access matches an address in the cache and the valid bit for that
word is set, data is fetched from the cache. When the valid bit is cleared, data is accessed from the eSRAM
or from external memory and stored in the cache, and the valid bit is set. The cache is cleared only by
writing 1 to the CACHE CLR bit. This action also registers the base address of the 2K boundary as the
valid cache block address. The user must program the MMA_MAC_XBASE register and the
MMA_MAC_XINDEX register before clearing the cache.
MOTOROLA
Base Register
Points to the start
address of the circular
buffer.
Address Index
Base register added
to Index register to
produce Address
Index
Modify Register
This value is added to the
Address Index after each
access.
Length Register
Determines the size of the circular buffer. Actual
Index = (index - length). Actual physical location
is (Actual Index + Base)
Figure 17-2. Circular Buffering Operation
Multimedia Accelerator (MMA)
+
INDEX_LOAD
+
MMA Operation
eSRAM
17-3
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