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Reset Operation
28.8.3.2 CFG_CHG
When the device receives a CFG_CHG interrupt, the module NAKs all traffic from the USB host until
software clears the interrupt bit. This prevents the device configuration from getting out of sync with what
the host has requested.
28.8.3.3 EOT
When an end-of-transfer is received on a BULK OUT endpoint, the device NAKs all traffic on that
endpoint until software clears the interrupt bit. This prevents data from two different transfers from
becoming mixed up in a FIFO.
28.8.3.4 DEVREQ
When a device request is received, the device NAKs all IN/OUT traffic on the affected endpoint until
software clears the interrupt bit. This ensures that the device correctly identifies the setup packet in the
FIFO and can clear the FIFO before the data phase is allowed to begin. When multiple setup packets are
received, the MDEVREQ interrupt asserts.
28.9 Reset Operation
The USB module includes four reset modes: Hard Reset, Software Reset, UDC reset and USB Reset
signaling.
The UDC reset allows software to force a hard reset of the UDC module only, leaving all register bits in
the front-end logic intact. A UDC reset is normally used only as a debug option, however it can also be
used in the event of a connect/disconnect bus event. A hard reset requires that MCU PLL and System PLL
be locked.
28.9.1 Hard Reset
A hard reset is generated from the USB module's bus interface, and resets all storage elements in both the
front-end logic and in the UDC module. A hard reset also issues a UDC reset. Both the MCU PLL and
System PLL must be locked before issuing a Software Reset.
28.9.2 USB Software Reset
The USB device allows the reset of all the storage elements in both the front-end logic and in the UDC
module through the RST bit in the USB_ENAB register. On initial power-up, the user issues a Software
reset. This causes the module to be enabled and the internal logic to be reset. Both the MCU PLL and USB
PLL must be locked before issuing a Software Reset.
28.9.3 UDC Reset
A UDC reset is accomplished by setting the UDC_RST bit in the USB Control Register (USB_CTRL.)
The UDC must be reset any time a connect/disconnect occurs on the USB. Any time the device is plugged
in or unplugged from the USB, software must initiate either a hard reset or a UDC reset to ensure that the
module can properly communicate with the USB host. Reset signaling is discussed in chapter 7 of the USB
Specification. UDC Reset can invalidate data remaining in the data FIFOs. Depending on the application,
software might need to flush the data FIFOs before proceeding.
MOTOROLA
USB Device Port
28-47
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