Timer Prescaler Registers 1 And 2; Table 26-4 Timer 1 And 2 Prescaler Registers Description - Motorola DragonBall MC9328MX1 Reference Manual

Table 26-3. Timer 1 and 2 Control Registers Description (Continued)
Name
IRQEN Interrupt Request Enable—Enables/Disables the
Bit 4 generation of an interrupt on a compare event.
CLKSOURCE Clock Source—Selects the source of the clock to the
Bits 3–1 prescaler. The stop-count setting freezes the timer at its
current value.
TEN Timer Enable—Enables/Disables the general-purpose
Bit 0 timer. The TEN bit can be reset only by a hardware
asynchronous reset, not by the SWR reset.
Note: When configuring this control register, configure
all other bits before configuring the TEN bit.

26.2.2 Timer Prescaler Registers 1 and 2

Each timer prescaler register (TPRER1 and TPRER2) controls the divide ratio of the associated 8-bit
prescaler. The settings for the registers are described in Table 26-4.
TPRER1
TPRER2
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
TYPE r r r
0 0 0
RESET
Table 26-4. Timer 1 and 2 Prescaler Registers Description
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–8
PRESCALER Prescaler—Determines the division value (1–256) of the prescaler.
Bits 7–0
MOTOROLA
Description
Timer 1 Prescaler Register
Timer 2 Prescaler Register
28 27 26 25
r r r r
0 0 0 0
12 11 10 9
r r r r
0 0 0 0
Description
General-Purpose Timers
0 = Disable the compare interrupt
1 = Enable the compare interrupt
000 = Stop count (clock disabled)
001 = PERCLK1 to prescaler
010 = PERCLK1 ÷16 to prescaler
011 = TIN to prescaler
1xx = 32 kHz clock to prescaler
0 = Timer is disabled (counter reset to
0x00000000)
1 = Timer is enabled
24 23 22 21 20
r r r r r
0 0 0 0 0
0x0000
8 7 6 5 4
PRESCALER
r rw rw rw rw
0 0 0 0 0
0x0000
Programming Model
Settings
Addr
0x00202004
0x00203004
19 18 17 16
r r r r
0 0 0 0
3 2 1 0
rw rw rw rw
0 0 0 0
Settings
0x00 = Divide by 1
0x01 = Divide by 2
...
0xFF = Divide by 256
26-5