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DMA Controller
13.4.2.3 Y-Size Registers
The Y-Size registers (YSRA and YSRB) contain the number of rows in the 2D memory window. This
setting is used by the DMA controller to calculate the total size of the transfer.
YSRA
YSRB
BIT
31
30
29
TYPE
r
r
r
0
0
0
RESET
BIT
15
14
13
TYPE
rw
rw
rw
0
0
0
RESET
Name
Reserved
Reserved—These bits are reserved and should read 0.
Bits 31–16
YS
Y-Size—Contains the number of rows that make up the 2D memory window.
Bits 15–0
13.4.3 Channel Registers
Channels 0 to 10 support linear memory, 2D memory, FIFO, and end-of-burst enable FIFO transfer. Only
one enabled channel may be configured for 2D memory at any time.
The interrupt request DMA_REQ [31:0] does not have a priority assigned. The only priority available is
the priority that is defined for each channel: channel 10 has the highest priority and channel 0 has the
lowest priority. Channel priority is implemented only when more than one request occurs at the same time,
otherwise, channels are serviced on a first come, first serve basis.
Each channel generates a normal interrupt to the interrupt handler when the data count reaches the selected
value and the channel source mode is not set to end-of-burst enable FIFO.
Each channel generates an error interrupt to the interrupt handler when the following conditions exist:
•
A DMA request time-out is true
•
A DMA burst time-out is true during a burst cycle
•
The internal buffer overflows during a burst cycle
•
A transfer error acknowledge is asserted during a burst cycle
13-18
Y-Size Register A
Y-Size Register B
28
27
26
25
r
r
r
r
0
0
0
0
12
11
10
9
rw
rw
rw
rw
0
0
0
0
Table 13-13. Y-Size Registers Description
MC9328MX1 Reference Manual
24
23
22
21
20
r
r
r
r
r
0
0
0
0
0
0x0000
8
7
6
5
4
YS
rw
rw
rw
rw
rw
0
0
0
0
0
0x0000
Description
Addr
0x00209048
0x00209054
19
18
17
16
r
r
r
r
0
0
0
0
3
2
1
0
rw
rw
rw
rw
0
0
0
0
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