Introduction - Motorola DragonBall MC9328MX1 Reference Manual

Chapter 4
ARM920T Processor
This chapter describes the operational features of the ARM920T™ high-performance processor that
includes an overall summary of both the ARM920T processor core and the Thumb® instruction set as well
as the operational modes. For detailed technical and programming information about the ARM920T
processor refer to the ARM920T Technical Reference Manual (ARM Limited: 2001, order number
DDI 0151C).

4.1 Introduction

The ARM920T processor is a high-performance 32-bit RISC integer processor macrocell combining an
ARM9TDMI™ core with:
• 16 kbit instruction and 16 kbit data caches
• Instruction and data Memory Management Units (MMUs)
• Write buffer
• AMBA™ (Advanced Microprocessor Bus Architecture) bus interface
• Embedded Trace Macrocell (ETM) interface.
An enhanced ARM® architecture v4 MMU implementation provides translation and access permission
checks for instruction and data addresses. The ARM920T high-performance processor solution gives
considerable savings in chip complexity and area, chip system design, and power consumption. The
ARM920T processor is 100% user code binary compatible with ARM7TDMI
compatible with the ARM7™ Thumb® Family and the StrongARM
software-compatible processors with a range of price/performance points from 60 MIPS to 200+ MIPS.
MOTOROLA ARM920T Processor
®
, and backwards
®
processor families, giving designers
4-1