Dtr—Data Terminal Ready; Dtr Edge Triggered Interrupt; Table 27-5 Dtr Edge Triggered Interrupt Truth Table - Motorola DragonBall MC9328MX1 Reference Manual

Table 27-4. RTS Edge Triggered Interrupt Truth Table (Continued)
RTS RTSEN RTEC [1]
1–>0 1
0–>1 1
There is another RTS interrupt that is not programmable, however it asserts the RTS Delta (RTSD) bit
when the RTS pin changes state. The status bit RTSD asserts the UART_MINT_RTS interrupt when the
RTS delta interrupt enable = 1. This is an asynchronous interrupt. The RTSD bit is cleared by writing 1 to
it. Writing 0 to the RTSD bit has no effect.
27.4.3 DTR—Data Terminal Ready
The data terminal ready signal to the UART2_DTR indicates the general readiness of the data terminal
equipment (DTE). When the connection between the UART and the DTE is established, the DTR signal
must remain active throughout the whole connection time. The DTR signal is only available on UART2. In
general, the DTR and DSR signals establish the connection and the RTS and CTS signals control the data
transfer and the transfer direction (for half-duplex configurations). The DTR signal is like a main
switch—when the DTR signal is inactive the RTS and CTS signals have no effect and the modem does not
respond to control signals. This functionality is not implemented in the hardware and is the result of how
the registers in the UART are programmed.

27.4.4 DTR Edge Triggered Interrupt

The DTR signal can be used to generate an interrupt on a selectable edge. To enable the DTR signal to
generate an interrupt, set the data terminal ready interrupt enable (DTREN) bit in UART Control Register
3 (UCR3_1/UCR3_2). Clear the DTRF bit by writing 1 to it. Writing 0 to the DTRF bit has no effect.
Write to the DTR interrupt edge control (DPEC) field in UCR3_1/UCR3_2 to select the edge that
generates an interrupt. When the DPEC field is set to 00b and DTREN = 1, the interrupt occurs on the
rising edge (default). When the bits are set to 01b and DTREN = 1, the interrupt occurs on the falling edge.
When the bits are set to 1Xb and DTREN = 1, the interrupt occurs on either edge. This is a synchronous
interrupt.
Table 27-5. DTR Edge Triggered Interrupt Truth Table
DTR DTREN DPEC [1]
X 0
1–>0 1
0–>1 1
1–>0 1
0–>1 1
1–>0 1
0–>1 1
MOTOROLA Universal Asynchronous Receiver/Transmitters (UART) Modules
RTEC [0] RTSF
1 X 1
1 X 1
DPEC [0] DTRF
X X 0
0 0 0
0 0 1
0 1 1
0 1 0
1 X 1
1 X 1
General UART Definitions
Interrupt Occurs On...
Either edge
Either edge
Interrupt Occurs On...
Interrupt disabled
Rising edge
Rising edge
Falling edge
Falling edge
Either edge
Either edge
UART_MINT_RTS
0
0
UART_MINT_DTR
1
1
0
0
1
0
0
27-7