Motorola DragonBall MC9328MX1 Reference Manual page 608

SDRAM Memory Controller
Table 24-7. SDRAM 0 Control Register and SDRAM 1 Control Register Description (Continued)
Name
SP Supervisor Protect—Restricts user accesses within
Bit 27 the chip-select region.
Reserved Reserved—This bit is reserved and should read 0.
Bit 26
ROW Row Address Width—Specifies the number of row
Bits 25–24 addresses used by the memory array. This number
does not include the bank, column, or data qualifier
addresses. Parameters affected by the programming of
this field include the page-hit address comparators and
the bank address bit locations (non-interleaved mode
only).
Reserved Reserved—These bits are reserved and should read 0.
Bits 23–22
COL Column Address Width—Specifies the number of
Bits 21–20 column addresses in the memory array and will
determine the break point in the address multiplexer.
Column width is the number of multiplexed column
addresses and does not include bank and row
addresses, or addresses used to generate the DQM
signals.
24-10
Description
MC9328MX1 Reference Manual
Settings
0 = User mode accesses are allowed to
this chip-select region.
1 = User mode accesses are prohibited.
An attempted access to this
chip-select region while in user
mode will result in a BUS ERROR
being returned back to the CPU. The
chip-select will not be asserted.
Read Accesses are not affected.
00 = 11
01 = 12
10 = 13
11 = Reserved
00 = 8
01 = 9
10 = 10
11 = 11
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