Motorola DragonBall MC9328MX1 Reference Manual page 219

Table 11-5. Chip Select Control Registers Description (Continued)
Name
CNC Chip Select Negation Clock Cycles—Specifies
Bits 47–46 the minimum number of clock cycles a chip select
must remain negated after it is negated.
CNC has no effect on write accesses when any
CSA bit is set.
CNC is cleared by a hardware reset.
WSC Wait State Control—
Bits 45–40 For SYNC = 0:
WSC programs the number of wait-states for an
access to the external device connected to the
chip select. Table 11-6, "Chip Select Wait State
and Burst Delay Encoding" shows the encoding of
this field. When WWS is cleared, setting:
•
•
•
•
•
For SYNC = 1:
WSC programs the number of system clock
cycles required for the initial access of a burst
sequence initiated by the EIM to an external burst
device. See Table 11-6, "Chip Select Wait State
and Burst Delay Encoding" and to the EIM
synchronous burst read timing diagrams for
further details.
to, the WSC
WSC is set to 111110 by a hardware reset for
CS0.
WSC is cleared by a hardware reset for
CS1–CS5.
Reserved Reserved—This bit is reserved and should read 0.
Bit 39
WWS Write Wait State—Determines whether
Bits 38–36 additional wait-states are required for write
cycles. This is useful for writing to memories that
require additional data setup time.
WWS is cleared by a hardware reset.
MOTOROLA
Description
WSC = 000000 results in 2 clock
transfers
WSC = 000001 results in 2 clock
transfers
WSC = 001110 results in 15 clock
transfers
WSC = 111110 results in 63 clock
transfers
WSC=111111 selects DTACK input
functionality for CS5
External Interface Module (EIM)
Programming Model
Settings
00 = Minimum negation is 0 clock cycles
01 = Minimum negation is 1 clock cycle
10 = Minimum negation is 2 clock cycles
11 = Minimum negation is 3 clock cycles
See Table 11-6, "Chip Select Wait State and
Burst Delay Encoding"
See Table 11-6, "Chip Select Wait State and
Burst Delay Encoding"
11-15