Pwm Contrast Control Register; Table 19-20 Pwm Contrast Control Register Description - Motorola DragonBall MC9328MX1 Reference Manual

LCD Controller

19.4.12 PWM Contrast Control Register

The PWM Contrast Control Register is used to control the signal output at the CONTRAST pin, which
controls the contrast of the LCD panel.
PWMR
BIT 31 30 29
TYPE r r r
0 0 0
RESET
BIT 15 14 13
LD
MSK
TYPE rw r r
0 0 0
RESET
Table 19-20. PWM Contrast Control Register Description
Name
Reserved Reserved—These bits are reserved and should read 0.
Bits 31–25
CLS_HI_ CLS High Pulse Width—Controls the Hi Pulse width of CLS in units of SCLK. The actual pulse width
WIDTH = CLS_HI_WDITH +1.
Bit 24–16
LDMSK LD Mask—Enables/Disables the LD output to zero for the Sharp
Bit 15 TFT panel power-off sequence.
Reserved Reserved—These bits are reserved and should read 0.
Bits 14–11
SCR Source Select—Selects the input clock source for the PWM
Bits 10–9 counter. The PWM output frequency is equal to the frequency of the
input clock divided by 256.
CC_EN Contrast Control Enable—Enables/Disables the contrast control
Bit 8 function.
PW Pulse-Width—Controls the pulse-width of the built-in pulse-width modulator, which controls the
Bits 7–0 contrast of the LCD screen.
19-32
PWM Contrast Control Register
28 27 26 25
r r r r
0 0 0 0
12 11 10 9
SCR
r r rw rw
0 0 0 0
Description
MC9328MX1 Reference Manual
24 23 22 21
CLS_HI_WIDTH
rw rw rw rw
0 0 0 0
0x0000
8 7 6 5
CC_EN
rw rw rw rw
0 0 0 0
0x0000
0 = LD [15:0] is normal
1 = LD [15:0] always equals 0
00 = Line pulse
01 = Pixel clock
10 = LCD clock
11 = Reserved
0 = Contrast control is off
1 = Contrast control is on
Addr
0x0020502C
20 19 18 17 16
rw rw rw rw rw
0 0 0 0 0
4 3 2 1 0
PW
rw rw rw rw rw
0 0 0 0 0
Settings
MOTOROLA